AM29LV065DU90REF Spansion Inc., AM29LV065DU90REF Datasheet - Page 27

• Manufacturer Part Number: AM29LV065DU90REF
• Description: Flash Memory IC
• Manufacturer: Spansion Inc.

Specifications of AM29LV065DU90REF

• Memory Size: 64Mbit
• Memory Configuration: 8M X 8
• Ic Interface Type: Parallel
• Access Time: 90ns
• Memory Case Style: TSOP
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +85°C
• Termination Type: SMD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations.
shows the address and data requirements for the chip
erase command sequence.
When the Embedded Erase algorithm is complete, the
device returns to the read mode and addresses are no
longer latched. The system can determine the status
of the erase operation by using DQ7, DQ6, DQ2, or
RY/BY#. Refer to the Write Operation Status section
for information on these status bits.
Any commands written during the chip erase operation
are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. The SecSi
Sector, autoselect, and CFI functions are unavailable
when an erase operation is in progress. If that occurs,
the chip erase command sequence should be reiniti-
ated once the device has returned to reading array
data, to ensure data integrity.
Figure 5
tion. Refer to the Erase and Program Operations ta-
bles in the AC Characteristics section for parameters,
and
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two ad-
ditional unlock cycles are written, and are then fol-
lowed by the address of the sector to be erased, and
the sector erase command.
dress and data requirements for the sector erase com-
mand sequence.
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm auto-
matically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations.
After the command sequence is written, a sector erase
time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
tors may be from one sector to all sectors. The time
February 16, 2006
Figure 18
illustrates the algorithm for the erase opera-
section for timing diagrams.
Table 10
shows the ad-
Table 10
Am29LV065D
between these additional cycles must be less than 50
µs, otherwise erasure may begin. Any sector erase ad-
dress and command following the exceeded time-out
may or may not be accepted. It is recommended that
processor interrupts be disabled during this time to en-
sure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. Any command other than Sector Erase or
Erase Suspend during the time-out period resets
the device to the read mode. The system must re-
write the command sequence and any additional ad-
dresses and commands.
The system can monitor DQ3 to determine if the sec-
tor erase timer has timed out (See the section on DQ3:
Sector Erase Timer.). The time-out begins from the ris-
ing edge of the final WE# pulse in the command
sequence.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses
are no longer latched. Note that while the Embedded
Erase operation is in progress, the system can read
data from the non-erasing sector. The system can de-
termine the status of the erase operation by reading
DQ7, DQ6, DQ2, or RY/BY# in the erasing sector.
Refer to the Write Operation Status section for infor-
mation on these status bits.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. The SecSi Sector,
autoselect, and CFI functions are unavailable when an
erase operation is in progress. All other commands
are ignored. However, note that a hardware reset im-
mediately terminates the erase operation. If that oc-
curs, the sector erase command sequence should be
reinitiated once the device has returned to reading
array data, to ensure data integrity.
Figure 5
tion. Refer to the Erase and Program Operations ta-
bles in the AC Characteristics section for parameters,
and
Erase Suspend/Erase Resume
Commands
The Erase Suspend command, B0h, allows the sys-
tem to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected
for erasure. This command is valid only during the sec-
tor erase operation, including the 50 µs time-out pe-
riod during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program
algorithm.
When the Erase Suspend command is written during
the sector erase operation, the device requires a max-
imum of 20 µs to suspend the erase operation. How-
ever, when the Erase Suspend command is written
Figure 18
illustrates the algorithm for the erase opera-
section for timing diagrams.
27