AM29F002BT-70JC Spansion Inc., AM29F002BT-70JC Datasheet - Page 4

• Manufacturer Part Number: AM29F002BT-70JC
• Description: Flash Memory IC
• Manufacturer: Spansion Inc.

Specifications of AM29F002BT-70JC

• Memory Size: 2Mbit
• Memory Configuration: 256K X 8
• Ic Interface Type: Parallel
• Access Time: 70ns
• Memory Case Style: PLCC
• No. Of Pins: 32
• Operating Temperature Range: 0°C To +70°C
• Termination Type: SMD

GENERAL DESCRIPTION
T h e A m2 9 F0 0 2 B F a mi l y c o n si s ts o f 2 M b it , 5 .0
vol t-o nly Fla sh memo ry d evices o rga nized as 262 ,144
b yte s. The A m2 9F00 2B o ffe rs th e RES ET# fu nctio n,
th e A m 2 9F 00 2 NB d oe s n o t. T h e d a ta a p pe a r s on
DQ 7 – DQ 0 . Th e d e vic e i s offe r ed in 3 2- p in P LC C,
3 2-p in TSO P, an d 32 -pi n PDIP p ackag es. Th is device
is d esig ned to be pro gra mmed in- system with the stan-
d ard system 5.0 vo lt V
wri te o r era se op era tio ns. The de vice can a lso be p ro-
g ramme d in stand ard E PRO M pro gra mmers.
Th is d evi ce i s ma nu fac tur ed us in g A MD’s 0 .3 2 µ m
p rocess techn olo gy, and offe rs all th e featur es an d b en-
e fits of th e Am2 9F00 2, which was man ufa ctu red using
0 .5 µ m p roce ss techn olo gy.
The sta nda rd de vi ce o ffer s a cce ss times of 55 , 70 , 9 0,
a nd 1 20 n s, all owin g hi gh spe ed m icro pro cesso rs to
o pera te witho ut wait sta tes. To elimi nate b us con te ntion
th e de vi ce ha s se p a ra te ch ip e n ab l e (CE # ) , w r ite
e nabl e (WE #) an d ou tp ut e na ble ( O E#) co ntro ls.
Th e de vic e r eq u ir e s on l y a s ingle 5.0 vo lt pow e r
s upply for b o th re ad a n d wr ite fu ncti on s. In ter n all y
g ene rated and reg ula ted volta ges a re p rovide d for the
p rogr am an d era se o pe ration s.
The device is en ti rely co mmand set comp atible with the
J EDE C single-pow er- supply Flas h st andard. Com-
m an d s a re wr it ten to the co mm a nd re g i ste r u si ng
stan da rd micro pro cesso r wr ite ti ming s. Reg ister con -
ten ts ser ve as inp ut to an in te rn al sta te -ma chin e th at
co ntr ol s th e er ase a n d pr og ra mmi ng ci rcu itr y. W rite
cycles a lso i nter nal ly latch add resse s and d ata n ee ded
for the pro gr amm ing a n d era se op e ratio n s. Rea di ng
d ata o ut o f th e device is simil ar to re adi ng fr om other
Fla sh or EP ROM device s.
Device p rog rammi ng o ccu rs by exe cu ting the pro gra m
co mm a nd se qu e nc e. Th is i ni tia te s th e E m be dde d
P rogra m a lgo ri th m— an i nter na l alg or ith m tha t a uto -
ma ti ca lly time s the p rogr am pul se wid ths a nd veri fie s
p rop er cell ma rgin .
D e vi c e e r a s u r e o cc u r s b y ex e c u ti n g th e e r a se
co mm a nd se qu e nc e. Th is i ni tia te s th e E m be dde d
2
C C
supp ly. No V
PP
is req uire d for
Am 29 F002 B/Am 29 F00 2NB
E rase a lgo rithm— an in te rn al alg orith m that autom ati-
c a l l y p r e p r o g r a ms th e a r r a y ( i f i t is n o t a l r e a d y
p ro gr am med ) b efor e exe cutin g th e er ase o pe ra tio n.
Du rin g era se, the d evice auto matically times th e era se
p ulse wid ths a nd ver ifies pro per ce ll marg in.
T he ho st syste m ca n d ete ct wh e the r a p r og ra m o r
e rase ope ratio n is com plete by rea din g the DQ7 (Da ta #
Po llin g) an d DQ6 (to ggle ) sta tus bit s. After a pr ogr am
o r e rase cycle h as be en comp leted , th e d evice i s rea dy
to re ad a rray data o r accept an other co mman d.
Th e s ect or erase archite cture a llows me mor y sectors
to be e rased an d rep rog ramme d with ou t affe ctin g th e
d a ta c on te n ts of o th er se cto rs. Th e d e vic e is fu l ly
e rase d when sh ipp ed fro m the factor y.
Hardw are data prot ection mea sure s inclu de a low VCC
d ete ctor th at a utoma tically in hibits write opera tions dur ing
p owe r tra nsiti on s. Th e hardw are s ec tor prot ec tion
featur e di sa bles b oth pr ogram and era se op eration s in
a ny co mbination of the se ctors of memor y. This can be
a chieved via progra mmin g eq uipment.
Th e Era se S uspe nd fea tu re e nab les the use r to p ut
e rase o n ho ld for an y p eri od o f time to re ad d ata from,
o r p rog ram data to, a ny se ctor that i s no t se lected fo r
e rasu re. Tru e ba ckgr oun d era se ca n th us be ach ieved.
Th e ha rdw are RE SE T# pin ter mina te s an y ope ratio n
i n pr og ress an d re sets th e in ter na l sta te mach in e to
r ead ing a rray data . The RE SE T# p in can b e tie d to th e
system re set circui tr y. A syste m rese t wo uld th us a lso
r eset the d evice, en abli ng th e system microp roce sso r
to re ad the bo ot-up firm wa re from th e Flash memo ry.
( This fea ture is no t avail able o n the A m29F0 02 NB.)
Th e system can place the device into th e standby mode .
Power co nsu mp tion is grea tly re duced in this mode.
A M D’s Fl a sh tec hn o lo g y co mb in e s ye a rs o f Fl as h
m e mo r y ma n ufa ctu r in g e xp er ie n ce t o p ro d uc e th e
h ighe st levels of qua lity, relia bility a nd cost effectiven ess.
Th e de vice ele ctrica lly er ases al l b its wi th in a se cto r
s imu lta ne ou sly via Fo wl er -No rd he im tu nn el in g. Th e
d ata is pro gra mmed u si ng ho t e lectron i njectio n.