AM29F002BT-70JC Spansion Inc., AM29F002BT-70JC Datasheet - Page 16

• Manufacturer Part Number: AM29F002BT-70JC
• Description: Flash Memory IC
• Manufacturer: Spansion Inc.

Specifications of AM29F002BT-70JC

• Memory Size: 2Mbit
• Memory Configuration: 256K X 8
• Ic Interface Type: Parallel
• Access Time: 70ns
• Memory Case Style: PLCC
• No. Of Pins: 32
• Operating Temperature Range: 0°C To +70°C
• Termination Type: SMD

D Q 7 o r D Q 6. S ee “W r ite O per ation Status ” fo r in fo rm a-
tion o n thes e s tatus bits .
A n y c o m m a n d s w r i tt e n to th e d e v i c e d u r i n g th e
E m b e dd ed P ro gr am A lg o ri thm a r e ig n or ed . On the
A m 29 F 002 B on ly, no te th at a h ar d wa r e re se t d ur ing
the se c to r era s e op era tio n im m e dia te ly te rm i nates the
o p e ra ti on . T he S e c to r E r a s e c om m a n d s e q ue n c e
s ho uld b e rein itiate d o nc e the de vi c e h as retur ne d to
re ad ing a rray data, to ens u re da ta i ntegr ity.
P rog ram m i ng is a llow e d in any se qu en ce a nd ac r os s
s e c to r b o un d ar i es . A b it ca n n o t b e p r o g r a m m e d
fr o m a “ 0” b a ck to a “ 1 ”. Atte m ptin g to do s o c an ha lt
the op era tio n and s et D Q 5 to “1 ”, or c aus e the D ata#
Po ll in g al go ri thm to in d ic ate th e o pe ra tio n w as s u c -
c e s s fu l. H ow ev er, a s u c c ee di ng re ad s h ow s tha t the
d ata i s s ti ll “ 0”. O nly era se o per ation s c an c onv er t a “0”
to a “1 ”.
No te:
program command sequence.
Chip Erase Command Seq uence
C h ip e ras e is a s ix -bu s- cy c le op era ti on. T h e c h ip eras e
c om m an d se qu en c e i s in itiate d b y w ri ti ng tw o unl oc k
1 4
Increment Address
See the appropriate Command Definitions table for
F ig u r e 2.
in progress
Embedded
algorithm
Program
P ro g r am Op e ra tio n
No
Command Sequence
Write Program
Last Address?
Programming
from System
Verify Data?
Completed
Data Poll
START
Yes
Yes
A m 29 F 002 B /A m 29 F 00 2N B
No
c y c le s, fo llow e d by a s et-up c om m a nd . Tw o add itiona l
u nlo ck w rite c y c les are th en fo llow e d by the c h ip era s e
c o m m an d, w hic h in tu rn invo k es th e Em bed de d Era s e
a lgo rith m . T he de vi c e d oe s
p rep rog ram pr ior to era se . T he E m be dde d Era se a lgo -
r ithm auto m atic ally pre pro gra m s an d ve rifies th e en tir e
m em or y for an al l z er o d ata pa tter n pr ior to e lec tri ca l
e ras e. T h e s y s te m is n ot req uir ed to pro vi de any c on -
tro ls or ti m ing s dur ing th es e ope ratio ns . T h e C o m m an d
D e finition s table s ho w s th e a dd res s an d d ata req uire -
m ents for the c h ip era s e c om m a nd s eq uen c e.
A n y c o m m a n d s w r i tt e n t o t h e c h i p d u r i n g th e
E m b e d d e d E r a s e a l g o r it hm a r e ig n o r e d . O n t h e
A m 2 9F 00 2B o nly, n ote th at a h a rd w ar e r es et du rin g
th e s ec tor e ras e o per ation i m m ed iately ter m ina te s th e
o p e ra ti o n . T h e S e c to r Er a s e c o m m a nd s e q u e nc e
s h ou ld be re initia te d on ce the d ev ic e ha s re tu rn ed to
r ead ing a rray da ta , to en s ure d ata integ rity.
T h e s y s te m c an dete rm in e the sta tu s of th e e ras e o pe r-
a ti o n b y u s in g D Q 7 , D Q 6 , o r D Q 2 . S e e
O pe ratio n S ta tu
W hen th e Em b edd ed E ras e a lgo rithm is c om p lete, th e
d ev ic e r etur ns to rea din g a rray d ata a nd ad dre s se s ar e
n o lon ge r latc hed .
F i gur e 3
tio n. Se e the Era s e/Pro gra m Op era tio ns tabl es in “AC
C h ara c te ris tic s ” for par am eter s, a nd to th e C h ip/Se c to r
E ras e O pe ration Ti m ing s for tim ing w av efor m s .
Sector Erase Com man d Sequence
S ec tor e ras e is a s ix bus cy c le o pe ratio n. T h e s e c to r
e ra s e c om m an d s eq ue nc e i s in itia ted b y w r itin g tw o
u n lo c k c y c le s , fo ll ow e d b y a s et- up c om m a nd . Tw o
a dd iti ona l un loc k w rite c y c le s a re th en follo w ed b y th e
a d dr e s s o f the s ec to r to b e e ra s e d, a nd th e s e c to r
e r a s e c o m m a nd . T he C o m m a n d D e fi ni ti o ns t ab l e
s ho w s t he a dd r e s s an d d ata r eq u ir e m e n ts for th e
s e c to r eras e c o m m an d se qu enc e .
T h e dev ic e d oes
th e m e m or y pr ior to e ras e. T h e Em b edd ed Era s e a lgo -
r ithm a utom a ti ca lly p rog ram s a nd ve rifies th e s e ctor fo r
a n al l z er o da ta p atter n pr ior to el ec tric a l era s e. T h e
s y s te m is n o t r eq u i re d to pr o v i de a n y c o n tro l s o r
tim i ngs du rin g th es e op era ti ons .
A fte r the c o m m and s e que nc e is w r itte n, a s ec tor era s e
tim e-o ut o f 5 0 µ s b eg ins . D u rin g the tim e- ou t pe rio d,
a d di tio na l s e c tor a d dr es s es a nd s ec to r e ra s e c o m -
m and s c a n be w ritte n. Lo adin g the s e c to r era se buffe r
c an b e d o ne in a ny s e q u en c e , an d the n um be r of
s e c to rs c a n be from on e s ec tor to all s ec tors . T h e ti m e
b etw ee n the se ad ditio nal c yc le s m us t be les s tha n 5 0
µ s , othe rw is e th e l as t ad dre s s an d c o m m an d m i ght not
b e a c c e p te d , a n d er a s u r e c a n b eg i n . It is r e c o m -
m en de d th at p ro c es s or in terr up ts b e d is a ble d d ur in g
th is tim e to e ns u re al l c o m m a nd s ar e ac c e pted . T h e
illu s tr ates th e alg ori th m for the er as e op era -
s” fo r in fo rm a tio n o n the s e s tatus b its.
no t
re qui re the s y s te m to pr epr ogr am
no t
re qui re th e sy s tem to
“ W r it e