ADV7180KCP32Z Analog Devices Inc, ADV7180KCP32Z Datasheet - Page 76

• Manufacturer Part Number: ADV7180KCP32Z
• Description: 10-bit 4x Oversampling SDTV Decoder
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7180KCP32Z

• Design Resources: Low Cost Differential Video Receiver Using ADA4851 Amplifier and ADV7180 Video Decoder (CN0060) Low Cost Video Multiplexer for Video Switching Using ADA4853-2 Op Amp with Disable Function (CN0076)
• Applications: Digital Cameras, Mobile Phones, Portable Video
• Voltage - Supply, Analog: 1.71 V ~ 1.89 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADV7180
MPU PORT DESCRIPTION
The ADV7180 supports a 2-wire (I
Two inputs, serial data (SDATA) and serial clock (SCLK), carry
information between the ADV7180 and the system I
controller. Each slave device is recognized by a unique address.
The ADV7180 I
the decoder and to read back the captured VBI data. The
ADV7180 has four possible slave addresses for both read and
write operations, depending on the logic level of the ALSB pin.
The four unique addresses are shown in Table 104. The ADV7180
ALSB pin controls Bit 1 of the slave address. By altering the
ALSB, it is possible to control two ADV7180s in an application
without the conflict of using the same slave address. The LSB
(Bit 0) sets either a read or write operation. Logic 1 corresponds to
a read operation, and Logic 0 corresponds to a write operation.
Table 104. I
ALSB
0
0
1
1
To control the device on the bus, a specific protocol must be
followed. First, the master initiates a data transfer by establishing a
start condition, which is defined by a high-to-low transition on
SDATA while SCLK remains high. This indicates that an address/
data stream follows. All peripherals respond to the start condition
and shift the next eight bits (the 7-bit address plus the R/ W bit).
The bits are transferred from MSB down to LSB. The peripheral
that recognizes the transmitted address responds by pulling the
data line low during the ninth clock pulse; this is known as an
acknowledge bit. All other devices withdraw from the bus at
this point and maintain an idle condition. The idle condition is
where the device monitors the SDATA and SCLK lines for the
start condition and the correct transmitted address. The R/ W
bit determines the direction of the data. Logic 0 on the LSB of
2
C Address for ADV7180
SEQUENCE
SEQUENCE
2
C port allows the user to set up and configure
R/W
0
1
0
1
WRITE
READ
S
S
S = START BIT
P = STOP BIT
SLAVE ADDR A(S)
SLAVE ADDR
Slave Address
0x40
0x41
0x42
0x43
2
C-compatible) serial interface.
SDATA
SCLK
LSB = 0
A(S)
START ADDR
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
S
SUB ADDR
SUB ADDR
1–7
2
C master
R/W
8
Figure 52. Read and Write Sequence
A(S)
A(S) S
ACK
Figure 51. Bus Data Transfer
9
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SUBADDRESS
SLAVE ADDR
DATA
1–7
LSB = 1
8
A(S)
A(S) = NO ACKNOWLEDGE BY SLAVE
A(M) = NO ACKNOWLEDGE BY MASTER
ACK
the first byte means that the master writes information to the
peripheral. Logic 1 on the LSB of the first byte means that the
master reads information from the peripheral.
The ADV7180 acts as a standard slave device on the bus. The
data on the SDATA pin is eight bits long, supporting the 7-bit
address plus the R/ W bit. The device has 249 subaddresses to
enable access to the internal registers. It, therefore, interprets
the first byte as the device address and the second byte as the
starting subaddress. The subaddresses auto-increment, allowing
data to be written to or read from the starting subaddress. A data
transfer is always terminated by a stop condition. The user can
also access any unique subaddress register on a one-by-one
basis without updating all the registers.
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, they cause an immediate jump
to the idle condition. During a given SCLK high period, the user
should only issue one start condition, one stop condition, or a
single stop condition followed by a single start condition. If an
invalid subaddress is issued by the user, the ADV7180 does not
issue an acknowledge and returns to the idle condition.
In auto-increment mode, if the user exceeds the highest
subaddress, the following action is taken:
•
•
9
A(S)
In read mode, the highest subaddress register contents
continue to be output until the master device issues a
no acknowledge. This indicates the end of a read. A no
acknowledge condition occurs when the SDATA line is
not pulled low on the ninth pulse.
In write mode, the data for the invalid byte is not loaded
into any subaddress register. A no acknowledge is issued by
the ADV7180, and the part returns to the idle condition.
1–7
DATA
DATA
8
DATA
ACK
A(M)
9
STOP
P
A(S) P
DATA
A(M) P