ADV7180KCP32Z Analog Devices Inc, ADV7180KCP32Z Datasheet - Page 26

• Manufacturer Part Number: ADV7180KCP32Z
• Description: 10-bit 4x Oversampling SDTV Decoder
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7180KCP32Z

• Design Resources: Low Cost Differential Video Receiver Using ADA4851 Amplifier and ADV7180 Video Decoder (CN0060) Low Cost Video Multiplexer for Video Switching Using ADA4853-2 Op Amp with Disable Function (CN0076)
• Applications: Digital Cameras, Mobile Phones, Portable Video
• Voltage - Supply, Analog: 1.71 V ~ 1.89 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADV7180
AD_SECAM_EN, Enable Autodetection of SECAM,
Address 0x07[6]
Setting AD_SECAM_EN to 0 (default) disables the autodetection
of SECAM.
Setting AD_SECAM_EN to 1 enables the detection of SECAM.
AD_N443_EN, Enable Autodetection of NTSC 4.43,
Address 0x07[5]
Setting AD_N443_EN to 0 disables the autodetection of NTSC
style systems with a 4.43 MHz color subcarrier.
Setting AD_N443_EN to 1 (default) enables the detection of
NTSC style systems with a 4.43 MHz color subcarrier.
AD_P60_EN, Enable Autodetection of PAL 60,
Address 0x07[4]
Setting AD_P60_EN to 0 disables the autodetection of PAL
systems with a 60 Hz field rate.
Setting AD_P60_EN to 1 (default) enables the detection of PAL
systems with a 60 Hz field rate.
AD_PALN_EN, Enable Autodetection of PAL N,
Address 0x07[3]
Setting AD_PALN_EN to 0 (default) disables the detection of
the PAL N standard.
Setting AD_PALN_EN to 1 enables the detection of the PAL N
standard.
AD_PALM_EN, Enable Autodetection of PAL M,
Address 0x07[2]
Setting AD_PALM_EN to 0 (default) disables the autodetection
of PAL M.
Setting AD_PALM_EN to 1 enables the detection of PAL M.
AD_NTSC_EN, Enable Autodetection of NTSC,
Address 0x07[1]
Setting AD_NTSC_EN to 0 (default) disables the detection of
standard NTSC.
Setting AD_NTSC_EN to 1 enables the detection of standard NTSC.
FREE_RUN
TIME_WIN
f
SC
TAKE f
LOCK
SC
LOCK INTO ACCOUNT
1
0
SELECT THE RAW LOCK SIGNAL
SRLS
FSCLE
Figure 19. Lock Related Signal Path
0
1
Rev. F | Page 26 of 116
COUNTER OUT OF LOCK
COUNTER INTO LOCK
FILTER THE RAW LOCK SIGNAL
CIL[2:0], COL[2:0]
AD_PAL_EN, Enable Autodetection of PAL B/D/I/G/H,
Address 0x07[0]
Setting AD_PAL_EN to 0 (default) disables the detection of
standard PAL.
Setting AD_PAL_EN to 1 enables the detection of standard PAL.
SFL_INV, Subcarrier Frequency Lock Inversion
This bit controls the behavior of the PAL switch bit in the SFL
(genlock telegram) data stream. It was implemented to solve
some compatibility issues with video encoders. It solves two
problems.
First, the PAL switch bit is only meaningful in PAL. Some
encoders (including Analog Devices encoders) also look at the
state of this bit in NTSC.
Second, there was a design change in Analog Devices encoders
from ADV717x to ADV719x. The older versions used the SFL
(genlock telegram) bit directly, whereas the newer ones invert
the bit prior to using it. The reason for this is that the inversion
compensated for the one line delay of an SFL (genlock telegram)
transmission.
As a result, for the ADV717x and ADV73xx encoders, the PAL
switch bit in the SFL (genlock telegram) must be 0 for NTSC to
work. For the ADV7190/ADV7191, ADV7192, and
video encoders, the PAL switch bit in the SFL must be 1 to work
in NTSC. If the state of the PAL switch bit is wrong, a 180° phase
shift occurs.
In a decoder/encoder back-to-back system in which SFL is used,
this bit must be set up properly for the specific encoder used.
SFL_INV, Subcarrier Frequency Lock Inversion,
Address 0x41[6]
Setting SFL_INV to 0 (default) makes the part SFL compatible
with the ADV717x and ADV73xx video encoders.
Setting SFL_INV to 1 makes the part SFL compatible with the
ADV7190/ADV7191, ADV7192, and ADV7194 video encoders.
Lock Related Controls
Lock information is presented to the user through Bits[1:0] of
the Status 1 register (see the Status 1[7:0], Address 0x10[7:0]
section). Figure 19 outlines the signal flow and the controls
available to influence the way the lock status information is
generated.
MEMORY
STATUS 1[0]
STATUS 1[1]
ADV7194