ADUC814BRU Analog Devices Inc, ADUC814BRU Datasheet - Page 18

• Manufacturer Part Number: ADUC814BRU
• Description: A/D Converter (A-D) IC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC814BRU

• Peak Reflow Compatible (260 C): No
• No. Of Bits: 12 Bit
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• No. Of Inputs: 6
• Features: +3V Or +5V Operation
• Package / Case: 28-TSSOP
• Rohs Status: RoHS non-compliant
• Core Processor: 8052
• Core Size: 8-Bit
• Speed: 16.78MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PSM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 640 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: EVAL-ADUC814QSZ - KIT DEV FOR ADUC814 MICROCONVRTR
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ADuC814
The SFR space is mapped to the upper 128 bytes of internal
data memory space and is accessed by direct addressing only. It
provides an interface between the CPU and all on-chip periph-
erals. A block diagram showing the programming model of the
ADuC814 via the SFR area is shown in Figure 21. A complete
SFR map is shown in Figure 22.
Program Status Word SFR
The program status word (PSW) register is the program status word that contains several bits reflecting the current status of the CPU as
detailed in Table 4.
SFR Address
Power-On Default
Bit Addressable
Table 4. PSW SFR Bit Designations
Bit No.
7
6
5
4
3
2
1
0
FLASH/EE PROGRAM
REPROGRAMMABLE
ELECTRICALLY
CY
NONVOLATILE
COMPATIBLE
256 BYTES
MEMORY
8-kBYTE
CORE
8051
RAM
Name
CY
AC
F0
RS1
RS0
OV
F1
P
Figure 21. Programming Model
AC
FUNCTION
REGISTER
128-BYTE
SPECIAL
AREA
D0H
00H
Yes
Description
Carry Flag.
Auxiliary Carry Flag.
General-Purpose Flag.
Register Bank Select Bits.
RS1
0
0
1
1
Overflow Flag.
General-Purpose Flag.
Parity Bit.
RS0
0
1
0
1
F0
REPROGRAMMABLE
DUAL 12-BIT DAC
FLASH/EE DATA
OTHER ON-CHIP
12-BIT SAR ADC
ELECTRICALLY
TEMPERATURE
NONVOLATILE
PERIPHERALS
6-CHANNEL
SERIAL I/O
640-BYTE
MONITOR
MEMORY
WDT
PSM
PLL
TIC
Selected Bank
0
1
2
3
RS1
Rev. A | Page 18 of 72
OVERVIEW OF MCU-RELATED SFRS
Accumulator SFR
ACC is the accumulator register and is used for math operations
including addition, subtraction, integer multiplication and
division, and Boolean bit manipulations. The mnemonics for
accumulator-specific instructions refer to the accumulator as A.
B SFR
The B register is used with the ACC for multiplication and
division operations. For other instructions it can be treated as a
general-purpose scratchpad register.
Stack Pointer SFR
The SP register is the stack pointer and is used to hold an internal
RAM address called the top of the stack. The SP register is
incremented before data is stored during PUSH and CALL
executions. While the stack may reside anywhere in on-chip
RAM, the SP register is initialized to 07H after a reset. This
causes the stack to begin at location 08H.
Data Pointer
The data pointer is made up of two 8-bit registers, named DPH
(high byte) and DPL (low byte). These registers provide memory
addresses for internal code access. The pointer may be manipu-
lated as a 16-bit register (DPTR = DPH, DPL), or as two inde-
pendent 8-bit registers (DPH, DPL).
RS0
OV
F1
P