ADUC7124BCPZ126-RL Analog Devices Inc, ADUC7124BCPZ126-RL Datasheet - Page 93

• Manufacturer Part Number: ADUC7124BCPZ126-RL
• Description: ARM7 With 12-Bit ADC & DACs, 128kB Flash
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7124BCPZ126-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 41.78MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 126KB (63K x 16)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 10x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 141. T1CON MMR Bit Descriptions
Bit
[31:18]
17
[16:12]
[11:9]
8
7
6
[5:4]
[3:0]
T1CLRI Register
Name:
Address:
Default Value:
Access:
T1CLRI is an 8-bit register. Writing any value to this register
clears the Timer1 interrupt.
T1CAP Register
Name:
Address:
Default Value:
Value
000
001
010
011
00
01
10
11
0000
0100
1000
1111
Description
Reserved.
Event select bit.
Set by the user to enable time capture of an
event.
Cleared by the user to disable time capture of an
event.
Event select range, 0 to 25. These events are as
described in Table 126. All events are offset by
two, that is, Event 2 in Table 126 becomes Event
0 for the purposes of Timer0.
Clock select.
Core clock (41 MHz/2
32.768 kHz.
UCLK.
P1.0 raising edge triggered.
Count up.
Set by the user for Timer1 to count up.
Cleared by the user for Timer1 to count down
by default.
Timer1 enable bit.
Set by the user to enable Timer1.
Cleared by the user to disable Timer1 by default.
Timer1 mode.
Set by the user to operate in periodic mode.
Cleared by the user to operate in free-running
mode. Default mode.
Format.
Binary.
Reserved.
Hr: min: sec: hundredths (23 hours to 0 hour).
Hr: min: sec: hundredths (255 hours to 0 hour).
Prescale.
Source clock/1.
Source clock/16.
Source clock/256.
Source clock/32,768.
T1CLRI
0xFFFF032C
0xFF
Write only
T1CAP
0xFFFF0330
0x00000000
CD
).
Rev. B | Page 93 of 104
Access:
T1CAP is a 32-bit register. It holds the value contained in
T1VAL when a particular event occurrs. This event must be
selected in T1CON.
Timer2 (Wake-Up Timer)
Timer2 is a 32-bit wake-up timer, count down or count up, with
a programmable prescaler. The prescaler is clocked directly from
one of four clock sources, including the core clock (default selec-
tion), the internal 32.768 kHz oscillator, the external 32.768 kHz
watch crystal, or the PLL undivided clock. The selected clock
source can be scaled by a factor of 1, 16, 256, or 32,768. The
wake-up timer continues to run when the core clock is disabled.
This gives a minimum resolution of 22 ns when the core is
operating at 41.78 MHz and with a prescaler of 1. Capture of
the current timer value is enabled if the Timer2 interrupt is
enabled via IRQEN[4] (see Table 126).
The counter can be formatted as a plain 32-bit value or as
hours: minutes: seconds: hundredths.
Timer2 reloads the value from T2LD either when Timer2
overflows or immediately when T2CLRI is written.
The Timer2 interface consists of four MMRs, shown in
Table 142.
Table 142. Timer2 Interface Registers
Register
T2LD
T2VAL
T2CLRI
T2CON
Timer2 Load Registers
Name:
Address:
Default Value:
Access:
T2LD is a 32-bit register, which holds the 32-bit value that is
loaded into the counter.
Timer2 Clear Register
Name:
Address:
Default Value:
Access:
This 8-bit write-only MMR is written (with any value) by user
code to refresh (reload) Timer2.
Description
32-bit register. Holds 32-bit unsigned integers.
32-bit register. Holds 32-bit unsigned integers. This
register is read only.
8-bit register. Writing any value to this register clears
the Timer2 interrupt.
Configuration MMR.
Read/write
T2LD
0xFFFF0340
0x00000
Read/write
T2CLRI
0xFFFF034C
0x00
Write only
ADuC7124/ADuC7126