ADUC7124BCPZ126-RL Analog Devices Inc, ADUC7124BCPZ126-RL Datasheet - Page 82

• Manufacturer Part Number: ADUC7124BCPZ126-RL
• Description: ARM7 With 12-Bit ADC & DACs, 128kB Flash
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7124BCPZ126-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 41.78MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 126KB (63K x 16)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 10x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7124/ADuC7126
PLACLK Register
Name:
Address:
Default Value:
Access:
PLACLK is the clock selection for the flip-flops of Block 0 and
Block 1. Note that the maximum frequency when using the
GPIO pins as the clock input for the PLA blocks is 41.78 MHz.
Table 120. PLACLK MMR Bit Descriptions
Bit
7
[6:4]
3
[2:0]
Table 122. Feedback Configuration
Bit
[10:9]
[8:7]
Value
000
001
010
011
100
101
110
111
000
001
010
011
100
101
Other
Value
00
01
10
11
00
01
10
11
Description
Reserved.
Block 1 clock source selection.
GPIO clock on P0.5.
GPIO clock on P0.0.
GPIO clock on P0.7.
HCLK.
OCLK (32.768 kHz).
Timer1 overflow.
UCLK.
Internal 32,768 oscillator.
Reserved.
Block 0 clock source selection.
GPIO clock on P0.5.
GPIO clock on P0.0.
GPIO clock on P0.7.
HCLK.
OCLK (32.768 kHz).
Timer1 overflow.
Reserved.
PLACLK
0xFFFF0B40
0x00
Read/write
PLAELM0
Element 15
Element 2
Element 4
Element 6
Element 1
Element 3
Element 5
Element 7
PLAELM1 to PLAELM7
Element 0
Element 2
Element 4
Element 6
Element 1
Element 3
Element 5
Element 7
Rev. B | Page 82 of 104
PLAIRQ Register
Name:
Address:
Default Value:
Access:
PLAIRQ enables IRQ0 and/or IRQ1 and selects the source
of the IRQ.
Table 121. PLAIRQ MMR Bit Descriptions
Bit
[15:13]
12
[11:8]
[7:5]
4
[3:0]
PLAELM8
Element 7
Element 10
Element 12
Element 14
Element 9
Element 11
Element 13
Element 15
Value
0000
0001
1111
0000
0001
1111
Description
Reserved.
PLA IRQ1 enable bit.
Set by the user to enable IRQ1 output from
PLA.
Cleared by the user to disable IRQ1 output
from PLA.
PLA IRQ1 source.
PLA Element 0.
PLA Element 1.
PLA Element 15.
Reserved.
PLA IRQ0 enable bit.
Set by the user to enable IRQ0 output from
PLA.
Cleared by the user to disable IRQ0 output
from PLA.
PLA IRQ0 source.
PLA Element 0.
PLA Element 1.
PLA Element 15.
PLAIRQ
0xFFFF0B44
0x00000000
Read/write
PLAELM9 to PLAELM15
Element 8
Element 10
Element 12
Element 14
Element 9
Element 11
Element 13
Element 15