ADUC7124BCPZ126-RL Analog Devices Inc, ADUC7124BCPZ126-RL Datasheet - Page 77

• Manufacturer Part Number: ADUC7124BCPZ126-RL
• Description: ARM7 With 12-Bit ADC & DACs, 128kB Flash
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7124BCPZ126-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 41.78MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 126KB (63K x 16)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 10x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-LFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
Name:
Address:
Default Value:
Access:
Function:
I
Name:
Address:
Default Value:
Access:
Function:
I
Name:
Address:
Default Value:
Access:
Function:
I
Name:
Addresses:
Default Value:
Access:
Function:
2
2
2
2
C Slave Device ID Registers
C Slave Receive Registers
C Slave Transmit Registers
C Hardware General Call Recognition Registers
I2C0SRX, I2C1SRX
0xFFFF0830, 0xFFFF0930
0x00
Read
This 8-bit MMR is the I
I2C0STX, I2C1STX
0xFFFF0834, 0xFFFF0934
0x00
Write
This 8-bit MMR is the I
I2C0ALT, I2C1ALT
0xFFFF0838, 0xFFFF0938
0x00
Read/write
This 8-bit MMR is used with hardware general
calls when I2CxSCON Bit 3 is set to 1. This
register is used in cases where a master is unable
to generate an address for a slave, and instead, the
slave must generate the address for the master.
I2C0IDx, I2C1IDx
0xFFFF093C = I2C1ID0
0xFFFF083C = I2C0ID0
0xFFFF0940 = I2C1ID1
0xFFFF0840 = I2C0ID1
0xFFFF0944 = I2C1ID2
0xFFFF0844 = I2C0ID2
0xFFFF0948 = I2C1ID3
0xFFFF0848 = I2C0ID3
0x00
Read/write
These 8-bit MMRs are programmed with I
bus IDs of the slave. See the I2C Bus Addresses
section for further details.
2
2
C slave receive register.
C slave transmit register.
2
Rev. B | Page 77 of 104
C
I
I
Name:
Address:
Default Value:
Access:
Function:
Table 111. I2CxFSTA MMR Bit Descriptions
Bit
[15:10]
9
8
[7:6]
[5:4]
[3:2]
[1:0]
2
2
C Common Registers
C FIFO Status Register
Name
I2CFMTX
I2CFSTX
I2CMRXSTA
I2CMTXSTA
I2CSRXSTA
I2CSTXSTA
I2C0FSTA, I2C1FSTA
0xFFFF084C, 0xFFFF094C
0x0000
Read/write
These 16-bit MMRs contain the status of the
Rx/Tx FIFOs in both master and slave modes.
Description
Reserved.
Set this bit to 1 to flush the master Tx
FIFO.
Set this bit to 1 to flush the slave Tx FIFO.
I
[00] = FIFO empty.
[01] = byte written to FIFO.
[10] = one byte in FIFO.
[11] = FIFO full.
I
[00] = FIFO empty.
[01] = byte written to FIFO.
[10] = one byte in FIFO.
[11] = FIFO full.
I
[00] = FIFO empty.
[01] = byte written to FIFO.
[10] = one byte in FIFO.
[11] = FIFO full.
I
[00] = FIFO empty.
[01] = byte written to FIFO.
[10] = one byte in FIFO.
[11] = FIFO full.
2
2
2
2
C master receive FIFO status bits.
C master transmit FIFO status bits.
C slave receive FIFO status bits.
C slave transmit FIFO status bits.
ADuC7124/ADuC7126