ADUC7060BSTZ32 Analog Devices Inc, ADUC7060BSTZ32 Datasheet - Page 68

DUAL 24-BIT AFE AND ARM 7 I.C

ADUC7060BSTZ32

Manufacturer Part Number
ADUC7060BSTZ32
Description
DUAL 24-BIT AFE AND ARM 7 I.C
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC7xxxr
Datasheets

Specifications of ADUC7060BSTZ32

Design Resources
4 mA-to-20 mA Loop-Powered Temperature Monitor Using ADuC7060/1 (CN0145) Low power, Long Range, ISM Wireless Measuring Node (CN0164)
Core Processor
ARM7
Core Size
16/32-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
14
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.375 V ~ 2.625 V
Data Converters
A/D 5x24b, 8x24b, D/A 1x14b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Cpu Family
ADuC7xxx
Device Core
ARM7TDMI
Device Core Size
16/32Bit
Frequency (max)
10.24MHz
Interface Type
I2C/SPI/UART
Total Internal Ram Size
4KB
# I/os (max)
14
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
2.5V
Operating Supply Voltage (max)
2.625V
Operating Supply Voltage (min)
2.375V
On-chip Adc
2(4-chx24-bit)
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Package
48LQFP
Family Name
ADuC7xxx
Maximum Speed
10.24 MHz
Operating Supply Voltage
2.5 V
Data Bus Width
16|32 Bit
Number Of Programmable I/os
14
Number Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant

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ADuC7060/ADuC7061
Timer0 Capture Register
Name:
Address:
Default value:
Access:
Function:
Timer0 Control Register
Name:
Address:
Default value:
Access:
Function:
Table 79. T0CON MMR Bit Designations
Bit
31:24
23
22:20
19
18
17
16:12
11
10:9
8
7
6
Name
T0PVAL
T0PEN
T0PCF
T0SRCI
T0CAPEN
T0CAPSEL
T0CLKSEL
T0DIR
T0EN
T0MOD
T0CAP
0xFFFF0330
0x00000000
Read only
This 32-bit register holds the 32-bit value captured by an enabled IRQ event.
T0CON
0xFFFF0328
0x01000000
Read and write
This 32-bit MMR configures the mode of operation of Timer0.
8-bit postscaler.
Timer0 enable postscaler.
Timer0 interrupt source.
Event Select Bits[17:0]. The events are described in Table 78.
Clock select.
Timer0 enable bit.
Description
By writing to these eight bits, a value is written to the postscaler. Writing 0 is interpreted as a 1.
By reading these eight bits, the current value of the counter is read.
Set to enable the Timer0 postscaler. If enabled, interrupts are generated after T0CON[31:24] periods
as defined by T0LD.
Cleared to disable the Timer0 postscaler.
Reserved. These bits are reserved and should be written as 0 by user code.
Postscaler compare flag; read only. Set if the number of Timer0 overflows is equal to the number written
to the postscaler.
Set to select interrupt generation from the postscaler counter.
Cleared to select interrupt generation directly from Timer0.
Event enable bit.
Set by user to enable time capture of an event.
Cleared by user to disable time capture of an event.
Reserved bit.
[00] = 32.768 kHz.
[01] = 10.24 MHz/CD.
[10] = 10.24 MHz.
[11] = P1.0.
Count up.
Set by user for Timer0 to count up.
Cleared by user for Timer0 to count down (default).
Set by user to enable Timer0.
Cleared by user to disable Timer0 (default).
Timer0 mode.
Set by user to operate in periodic mode.
Cleared by user to operate in free running mode (default).
Rev. C | Page 68 of 108

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