ADUC7036BCPZ-RL Analog Devices Inc, ADUC7036BCPZ-RL Datasheet - Page 42
ADUC7036BCPZ-RL
Manufacturer Part Number
ADUC7036BCPZ-RL
Description
Flash 96k ARM7 Dual 16-Bit ADC LIN I.C.
Manufacturer
Analog Devices Inc
Series
MicroConverter® ADuC7xxxr
Datasheet
1.EVAL-ADUC7036QSPZ.pdf
(132 pages)
Specifications of ADUC7036BCPZ-RL
Core Processor
ARM7
Core Size
16/32-Bit
Speed
20.48MHz
Connectivity
LIN, SPI, UART/USART
Peripherals
PSM, Temp Sensor, WDT
Number Of I /o
9
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 18 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 115°C
Package / Case
48-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADUC7036BCPZ-RL
Manufacturer:
ADI/亚德诺
Quantity:
20 000
ADuC7036
16-BIT, Σ-Δ ANALOG-TO-DIGITAL CONVERTERS
The ADuC7036 incorporates two independent Σ-Δ analog-to-
digital converters (ADCs): the current channel ADC (I-ADC)
and the voltage/temperature channel ADC (V-/T-ADC). These
precision measurement channels integrate on-chip buffering, a
programmable gain amplifier, 16-bit, Σ-Δ modulators, and
digital filtering for precise measurement of current, voltage,
and temperature variables in 12 V automotive battery systems.
CURRENT CHANNEL ADC (I-ADC)
The I-ADC converts battery current sensed through an external
100 μΩ shunt resistor. On-chip programmable gain means that
the I-ADC can be configured to accommodate battery current
levels from ±1 A to ±1500 A.
As shown in Figure 18, the I-ADC employs a Σ-Δ conversion
technique to attain 16 bits of no missing codes performance.
Rev. C | Page 42 of 132
The Σ-Δ modulator converts the sampled input signal into a
digital pulse train whose duty cycle contains the digital infor-
mation. A modified Sinc3, programmable, low-pass filter is
then used to decimate the modulator output data stream to give
a valid 16-bit data conversion result at programmable output
rates from 4 Hz to 8 kHz in normal mode and from 1 Hz to
2 kHz in low power mode.
The I-ADC also incorporates counter, comparator, and accu-
mulator logic. This allows the I-ADC result to generate an
interrupt after a predefined number of conversions has elapsed
or the I-ADC result exceeds a programmable threshold value.
A fast ADC overrange feature is also supported. Once enabled,
a 32-bit accumulator automatically sums the 16-bit I-ADC results.
The time to a first valid (fully settled) result on the current channel
is three ADC conversion cycles with chop mode disabled and
two ADC conversion cycles with chop mode enabled.