ADUC7036BCPZ-RL Analog Devices Inc, ADUC7036BCPZ-RL Datasheet
ADUC7036BCPZ-RL
Specifications of ADUC7036BCPZ-RL
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ADUC7036BCPZ-RL Summary of contents
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FEATURES High precision ADCs Dual channel, simultaneous sampling, 16-bit, Σ-Δ ADCs Programmable ADC throughput from kHz On-chip ±5 ppm/°C voltage reference Current channel Fully differential, buffered input Programmable gain from 1 to 512 ADC input range: ...
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ADuC7036 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications..................................................................................... 4 Electrical Specifications............................................................... 4 Timing Specifications ................................................................ 10 Absolute Maximum Ratings.......................................................... 15 ESD Caution................................................................................ 15 Pin Configuration and Function Descriptions........................... 16 ...
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REVISION HISTORY 2/11—Rev Rev. C Changes to I (MCU Normal Mode) Parameter, Table 1 ..........9 DD Changes to On-Chip Kernel Section ............................................32 Added Figure 16; Renumbered Sequentially ...............................34 Changes to Table 100 ....................................................................130 Changes to Ordering Guide.........................................................132 4/10—Rev. ...
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ADuC7036 SPECIFICATIONS ELECTRICAL SPECIFICATIONS VDD = 3 VREF = 1.2 V internal reference, f watch crystal or on-chip precision oscillator. All specifications T Table 1. Parameter Test Conditions/Comments ADC SPECIFICATIONS 1 Conversion Rate Chop off, ADC ...
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Parameter Test Conditions/Comments 13 Voltage Channel 1 No Missing Codes Valid at all ADC update rates 1 Integral Nonlinearity Chop off, 1 LSB = 439.5 μV Offset Error Chop on Offset Error Offset Error ...
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ADuC7036 Parameter Test Conditions/Comments VOLTAGE REFERENCE ADC Precision Reference Internal VREF 1 Power-Up Time 1 Initial Accuracy Measured Temperature Coefficient 22 Reference Long-Term Stability 23 External Reference Input Range 1 VREF Divide-by-2 Initial Error ADC ...
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Parameter Test Conditions/Comments 1 All logic inputs LOGIC INPUTS V , Input Low Voltage INL V , Input High Voltage INH 1 CRYSTAL OSCILLATOR Logic Inputs, XTAL1 Only V , Input Low Voltage INL V , Input High Voltage INH ...
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ADuC7036 Parameter Test Conditions/Comments R Slave termination resistance SLAVE 28 V Voltage drop at the serial diode, D SERIAL DIODE Symmetry of Transmit Propagation VDD (min Delay 1 Receive Propagation Delay VDD (min ...
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Parameter Test Conditions/Comments PACKAGE THERMAL SPECIFICATIONS 1 Thermal Shutdown , 31 Thermal Impedance (θ 48-lead LFCSP, stacked die JA POWER REQUIREMENTS Power Supply Voltages VDD (Battery Supply) 33 REG_DVDD, REG_AVDD Power Consumption 34 I (MCU Normal Mode) MCU ...
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ADuC7036 TIMING SPECIFICATIONS SPI Timing Specifications Table 2. SPI Master Mode Timing—Phase Mode = 1 Parameter Description 1 t SCLK low pulse width SCLK high pulse width SH t Data output valid after SCLK edge DAV t ...
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Table 3. SPI Master Mode—Phase Mode = 0 Parameter Description 1 t SCLK low pulse width SCLK high pulse width SH t Data output valid after SCLK edge DAV t Data output setup before SCLK edge DOSU ...
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ADuC7036 Table 4. SPI Slave Mode Timing—Phase Mode = 1 Parameter Description SCLK edge SCLK low pulse width SCLK high pulse width SH t Data output valid after SCLK edge DAV ...
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Table 5. SPI Slave Mode Timing (Phase Mode = 0) Parameter Description SCLK edge SCLK low pulse width SCLK high pulse width SH t Data output valid after SCLK edge DAV ...
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ADuC7036 LIN Timing Specifications RECESSIVE TRANSMIT (INPUT TO TRANSMITTING NODE) DOMINANT TH REC (MAX) TH DOM (MAX) V SUP (TRANSCEIVER SUPPLY OF TRANSMITTING NODE) TH REC (MIN) TH DOM (MIN) RxD (OUTPUT OF RECEIVING NODE 1) RxD (OUTPUT OF ...
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ABSOLUTE MAXIMUM RATINGS T = −40°C to +115°C, unless otherwise noted. A Table 6. Parameter Rating AGND to DGND to VSS to IO_VSS −0 +0.3 V VBAT to AGND − +40 V VDD to VSS −0.3 ...
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ADuC7036 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GPIO_5/IRQ1/RxD GPIO_6/TxD GPIO_7/IRQ4 GPIO_8/IRQ5 NOTES CONNECT. 2. THE EXPOSED PAD SHOULD BE CONNECTED TO DGND. Table 7. Pin Function Descriptions Pin No. Mnemonic Type 1 I RESET 2 GPIO_5/IRQ1/RxD I/O ...
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Pin No. Mnemonic Type 11 NTRST I 12 TMS I 13 VBAT I 14 VREF I 15 GND_SW I 18 VTEMP I 19 IIN IIN− I 21, 22 AGND S 24 REG_AVDD S 27 GPIO_0/IRQ0/SS I/O 28 GPIO_1/SCLK ...
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ADuC7036 TYPICAL PERFORMANCE CHARACTERISTICS 0 –0.2 VDD = 4V –0.4 –0.6 –0.8 –1.0 –1.2 –40 – TEMPERATURE (°C) Figure 8. ADC Current Channel Offset vs. Temperature, 10 MHz MCU 0 –40°C –0.5 +25°C –1.0 +115°C –1.5 –2.0 –2.5 ...
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TERMINOLOGY Conversion Rate The conversion rate specifies the rate at which an output result is available from the ADC after the ADC has settled. The Σ-Δ conversion techniques used on this part mean that while the ADC front-end signal is ...
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ADuC7036 THEORY OF OPERATION The ADuC7036 is a complete system solution for battery moni- toring automotive applications. These devices integrate all of the required features to precisely and intelligently monitor, process, and diagnose 12 V battery parameters, ...
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ARM7 Exceptions The ARM7 supports five types of exceptions with a privileged processing mode associated with each type. The five types of exceptions are as follows: • Normal interrupt or IRQ. This is provided to service general-purpose interrupt handling of ...
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ADuC7036 The minimum latency for FIQ or IRQ interrupts is five cycles. This consists of the shortest time the request can take through the synchronizer plus the time to enter the exception mode. Note that the ARM7TDMI initially (first instruction) ...
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Remap Operation When a reset occurs on the ADuC7036, execution starts automatically in the factory-programmed internal configuration code. This so-called kernel is hidden and cannot be accessed by user code. If the ADuC7036 is in normal mode, it executes the ...
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ADuC7036 RESET There are four kinds of resets: external reset, power-on reset, watchdog reset, and software reset. The RSTSTA register indicates the source of the last reset and can be written to by user code to initiate a software reset ...
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FLASH/EE MEMORY The ADuC7036 incorporates Flash/EE memory technology on chip to provide the user with nonvolatile, in-circuit reprogram- mable memory space. Like EEPROM, flash memory can be programmed in-system at a byte level, although it must first be erased, with ...
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ADuC7036 The FEE0CON and FEE1CON Registers section to the FEE0MOD and FEE1MOD Registers section provide detailed descriptions of the bit designations for each of the Flash/EE control MMRs. FEE0CON and FEE1CON Registers Name: FEE0CON and FEE1CON Address: 0xFFFF0E08 and 0xFFFF0E88 ...
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Command Sequence for Executing a Mass Erase Given the significance of the mass erase command, the following specific code sequence must be executed to initiate this operation: Set Bit 3 in FEExMOD. Write 0xFFC3 in FEExADR. Write 0x3CFF in FEExDAT. ...
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ADuC7036 FEE0DAT and FEE1DAT Registers Name: FEE0DAT and FEE1DAT Address: 0xFFFF0E0C and 0xFFFF0E8C Default Value: 0x0000 Access: Read/write access Function: This 16-bit register contains the data either read from written to the Flash/EE memory. Table 15. FEE0MOD ...
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FLASH/EE MEMORY SECURITY The Flash/EE memory available to the user can be read and write protected using the FFE0HID and FEE1HID registers. In Block 0, the FEE0HID MMR protects the 30 kB. Bits[0:28] of this register protect ...
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ADuC7036 Block 0, Flash/EE Memory Protection Registers Name: FEE0HID and FEE0PRO Address: 0xFFFF0E20 (for FEE0HID) and 0xFFFF0E1C (for FEE0PRO) Default Value: 0xFFFFFFFF (for FEE0HID) and 0x00000000 (for FEE0PRO) Access: Read/write access Function: These registers are written by user code to ...
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FLASH/EE MEMORY RELIABILITY The Flash/EE memory array on the part is fully qualified for two key Flash/EE memory characteristics: Flash/EE memory cycling endurance and Flash/EE memory data retention. Endurance quantifies the ability of the Flash/EE memory to be cycled through ...
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... HVDAT/HVCON • HVCFG0/HVCFG1 • T3LD The ADuC7036 also features an on-chip LIN downloader. The derivatives ADuC7036BCPZ and ADuC7036CCPZ use Protocol 4 for programming Flash/EE memory via LIN, where Protocol 6 is used on derivative ADuC7036DCPZ. The protocols are described in Application Note AN-881 (Protocol 4) and AN-946 (Protocol 6) ...
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... NTRST = 1 NO PAGE ERASED? KEY PRESENT? 0x14 = 0xFFFFFFFF 0x14 = 0x27011970 YES CHECKSUM PRESENT? 0x14 = CHECKSUM FLAG PAGE 0 ERROR NO YES RESET LIN COMMAND COMMAND Figure 15. ADuC7036BCPZ and ADuC7036CCPZ Kernel Flowchart Rev Page 33 of 132 YES YES NO YES EXECUTE USER CODE NO NO ADuC7036 ...
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ADuC7036 PAGE ERASED? 0x14 = 0xFFFFFFFF LIN COMMAND INITIALIZE ON-CHIP PERIPHERALS TO FACTORY- CALIBRATED STATE NO JTAG MODE? NTRST = 1 NO KEY PRESENT? 0x14 = 0x27011970 NO YES PAGE 0 CHECKSUM PRESENT? 0x14 = PG0-CKS NO BOOT LOADER NO ...
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MEMORY MAPPED REGISTERS The memory mapped register (MMR) space is mapped into the top the MCU memory space and accessed by indirect addressing, loading, and storage commands through the ARM7 banked registers. An outline of the memory ...
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ADuC7036 COMPLETE MMR LISTING In Table 19 to Table 30, addresses are listed in hexadecimal code. Access types include R for read, W for write, and RW for read and write. Table 19. IRQ Address Base = 0xFFFF0000 Access Address ...
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Access Address Name Byte Type 0x0340 T2LD 4 RW 0x0344 T2VAL 4 R 0x0348 T2CON 2 RW 0x034C T2CLRI 1 W 0x0360 T3LD 2 RW 0x0364 T3VAL 2 R 0x0368 T3CON 0x036C T3CLRI 1 W 0x0380 T4LD ...
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ADuC7036 Table 23. ADC Address Base = 0xFFFF0500 Access Address Name Byte Type 0x0500 ADCSTA 2 R 0x0504 ADCMSKI 1 RW 0x0508 ADCMDE 1 RW 0x050C ADC0CON 2 RW 0x0510 ADC1CON 2 RW 0x0518 ADCFLT 2 RW 0x051C ADCCFG 1 ...
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Table 24. UART Base Address = 0XFFFF0700 Access Address Name Byte Type 0x0700 COMTX 1 W COMRX 1 R COMDIV0 1 RW 0x0704 COMIEN0 1 RW COMDIV1 1 RW 0x0708 COMIID0 1 R 0x070C COMCON0 1 RW 0x0710 COMCON1 1 ...
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ADuC7036 Table 27. STI Base Address = 0xFFFF0880 Access Address Name Byte Type 0x0880 STIKEY0 4 W 0x0884 STICON 2 RW 0x0888 STIKEY1 4 W 0x088C STIDAT0 2 RW 0x0890 STIDAT1 2 RW 0x0894 STIDAT2 2 RW Table 28. SPI ...
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Table 30. Flash/EE Base Address = 0xFFFF0E00 Access Address Name Byte Type 0x0E00 FEE0STA 1 R 0x0E04 FEE0MOD 1 RW 0x0E08 FEE0CON 1 RW 0x0E0C FEE0DAT 2 RW 0x0E10 FEE0ADR 2 RW 0x0E18 FEE0SIG 3 R 0x0E1C FEE0PRO 4 RW ...
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ADuC7036 16-BIT, Σ-Δ ANALOG-TO-DIGITAL CONVERTERS The ADuC7036 incorporates two independent Σ-Δ analog-to- digital converters (ADCs): the current channel ADC (I-ADC) and the voltage/temperature channel ADC (V-/T-ADC). These precision measurement channels integrate on-chip buffering, a programmable gain amplifier, 16-bit, Σ-Δ modulators, ...
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Figure 18. Current ADC, Top-Level Overview Rev Page 43 of 132 ADuC7036 ...
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ADuC7036 Voltage/Temperature Channel ADC (V-/T-ADC) The voltage/temperature channel ADC (V-/T-ADC) converts additional battery parameters, such as voltage and temperature. The input to this channel can be multiplexed from one of three input sources: an external voltage, an external temperature sensor ...
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ADC GROUND SWITCH The ADuC7036 features an integrated ground switch pin, GND_SW (Pin 15). This switch allows the user to dynamically disconnect ground from external devices and, instead, use either a direct connection to ground or a connection to ground ...
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ADuC7036 ADC MMR INTERFACE The ADC is controlled and configured using several MMRs that are described in detail in the ADC Status Register section to the Low Power Voltage Reference Scaling Factor section. All bits defined in the top eight ...
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ADC Interrupt Mask Register Name: ADCMSKI Address: 0xFFFF0504 Default Value: 0x00 Access: Read/write Function: This register allows the ADC interrupt sources to be individually enabled. The bit positions in this register are the same as the lower eight bits in ...
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ADuC7036 Current Channel ADC Control Register Name: ADC0CON Address: 0xFFFF050C Default Value: 0x0000 Access: Read/write Function: This 16-bit register is used to configure the I-ADC. Note that if the current ADC is reconfigured via ADC0CON, the voltage ADC and temperature ...
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Voltage/Temperature Channel ADC Control Register Name: ADC1CON Address: 0xFFFF0510 Default Value: 0x0000 Access: Read/write Function: This 16-bit register is used to configure the V-/T-ADC. Note that when selecting the VBAT attenuator input, the voltage attenuator buffers are automatically enabled. Table ...
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ADuC7036 ADC Filter Register Name: ADCFLT Address: 0xFFFF0518 Default Value: 0x0007 Access: Read/write Function: This 16-bit register controls the speed and resolution of the on-chip ADCs. Note that if ADCFLT is modified, the current and voltage/temperature ADCs are reset. Table ...
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Table 40. ADC Conversion Rates and Settling Times Chop Enabled Averaging Factor Yes No Yes Yes N additional time of approximately 60 μs per ADC is required before the first ADC is available. ...
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ADuC7036 ADC Configuration Register Name: ADCCFG Address: 0xFFFF051C Default Value: 0x00 Access: Read/write Function: This 8-bit ADC configuration MMR controls extended functionality related to the on-chip ADCs. Table 42. ADCCFG MMR Bit Designations Bit Description 7 Analog ground switch enable. ...
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Current Channel ADC Data Register Name: ADC0DAT Address: 0xFFFF0520 Default Value: 0x0000 Access: Read only Function: This ADC data MMR holds the 16-bit conversion result from the I-ADC. The ADC does not update this MMR if the ADC0 conversion result ...
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ADuC7036 Voltage Channel ADC Gain Calibration Register Name: ADC1GN Address: 0xFFFF0540 Default Value: Part specific, factory programmed Access: Read/write Function: This gain MMR holds a 16-bit gain calibration coefficient for scaling a voltage channel conversion result. The register is configured ...
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Current Channel ADC Accumulator Register Name: ADC0ACC Address: 0xFFFF055C Default Value: 0x00000000 Access: Read only Function: This 32-bit MMR holds the current accumulator value. The I-ADC ready bit in the ADCSTA MMR should be used to determine when it is ...
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ADuC7036 ADC COMPARATOR AND ACCUMULATOR The incorporation of comparator logic on the I-ADC allows the I-ADC result to generate an interrupt after a predefined number of conversions has elapsed or a programmable threshold value has been exceeded. Every I-ADC result ...
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In ADC normal power mode, the maximum ADC throughput rate is 8 kHz. This is configured by setting the SF and AF bits in the ADCFLT MMR to 0, with all other filtering options disabled result, 0x0000 is ...
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ADuC7036 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 FREQUENCY (kHz) Figure 28. Typical Digital Filter Response at f ADC Table 43. Common ADCFLT Configurations ADC Mode SF AF Normal ...
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ADC CALIBRATION As shown in detail in the top-level diagrams (Figure 18 and Figure 19), the signal flow through all ADC channels can be described as follows input voltage is applied through an input buffer (and through PGA ...
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ADuC7036 The offset coefficient is read from the ADC0OF calibration register and is a 16-bit, twos complement number. The range of this number, in terms of the signal chain, is effectively ±1. Therefore, 1 LSB of the ADC0OF register is ...
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POWER SUPPLY SUPPORT CIRCUITS The ADuC7036 incorporates two on-chip low dropout (LDO) regulators that are driven directly from the battery voltage to generate a 2.6 V internal supply. This 2.6 V supply is then used as the supply voltage for ...
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ADuC7036 SYSTEM CLOCKS The ADuC7036 integrates a very flexible clocking system that allows clock generation from one of three sources: an integrated on-chip precision oscillator, an integrated on-chip low power oscillator external watch crystal. These three options are ...
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The operating mode, clocking mode, and programmable clock divider are controlled using two MMRs, PLLCON and POWCON, and the status of the PLL is indicated by PLLSTA. PLLCON controls the operating mode of the clock system, and POWCON controls both ...
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ADuC7036 PLLCON Prewrite Key Name: PLLKEY0 Address: 0xFFFF0410 Access: Write only Key: 0x000000AA Function: This keyed register requires a 32-bit key value to be written before and after PLLCON. PLLKEY0 is the prewrite key. PLLCON Postwrite Key Name: PLLKEY1 Address: ...
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POWCON Register Name: POWCON Address: 0xFFFF0408 Default Value: 0x79 Access: Read/write Function: This 8-bit register allows user code to dynamically enter various low power modes and modify the CD divider that controls the speed of the ARM7TDMI core. Table 46. ...
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ADuC7036 LOW POWER CLOCK CALIBRATION The low power 131 kHz oscillator can be calibrated using either the precision 131 kHz oscillator or an external 32.768 kHz watch crystal. Two dedicated calibration counters and an oscillator trim register are used to ...
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OSC0TRM Register Name: OSC0TRM Address: 0xFFFF042C Default Value: 0xX8 Access: Read/write Function: This 8-bit register controls the low power oscillator trim. Table 47. OSC0TRM MMR Bit Designations Bit Description Reserved. Should be written ...
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ADuC7036 PROCESSOR REFERENCE PERIPHERALS INTERRUPT SYSTEM There are 16 interrupt sources on the ADuC7036 that are con- trolled by the interrupt controller. Most interrupts are generated from the on-chip peripherals, such as the ADC and UART. The ARM7TDMI CPU core ...
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Normal Interrupt (IRQ) Request The IRQ request is the exception signal allowed to enter the processor in IRQ mode used to service general-purpose interrupt handling of internal and external events. All 32 bits of the IRQSTA MMR are ...
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ADuC7036 TIMER0 TIMER1 TIMER2 TIMER3 LIN H/W FLASH/EE PLL LOCK ADC UART SPI XIRQx TIMER0 TIMER1 TIMER2 TIMER3 TIMER4 LIN H/W FLASH/EE PLL LOCK ADC UART SPI XIRQx Figure 32. Interrupt Structure Rev Page 70 of 132 IRQ ...
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TIMERS The ADuC7036 features five general-purpose timer/counters. • Timer0, or the lifetime timer • Timer1, or general-purpose timer • Timer2, or the wake-up timer • Timer3, or the watchdog timer • Timer4, or the STI timer The five timers in ...
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ADuC7036 ARM7TDMI AMBA CORE CLOCK LOW POWER OSCILLATOR GPIO HIGH PRECISION OSCILLATOR XTAL CORE CLOCK (F ) CORE DOMAIN As shown in Figure 33, the MMR logic and core timer logic reside in separate and asynchronous clock domains. Any data ...
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Starting Timer2 When starting Timer2 recommended to first load Timer2 with the required TxLD value. Next, start the timer by setting the T2CON bits as required. This enables the timer, but only once the T2CON bits have been ...
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ADuC7036 TIMER0—LIFETIME TIMER Timer0 is a general-purpose, 48-bit up counter or a 16-bit up/down counter timer with a programmable prescaler. Timer0 can be clocked from either the core clock or the low power 32.768 kHz oscillator with a prescaler of ...
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Timer0 Control Register Name: T0CON Address: 0xFFFF030C Default Value: 0x00000000 Access: Read/write Function: This 32-bit MMR configures the mode of operation for Timer0. Table 53. T0CON MMR Bit Designations Bit Description Reserved. 17 Event select bit. Set ...
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ADuC7036 TIMER1—GENERAL-PURPOSE TIMER Timer1 is a general-purpose, 32-bit up/down counter with a programmable prescaler. The prescaler source can be the low power 32.768 kHz oscillator, the core clock, or from one of two external GPIOs. This source can be scaled ...
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Timer1 Capture Register Name: T1CAP Address: 0xFFFF0330 Default Value: 0x00000000 Access: Read only Function: This 32-bit register holds the 32-bit value captured by an enabled IRQ event. Table 54. T1CON MMR Bit Designations Bit Description 8-bit postscaler. ...
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TIMER2—WAKE-UP TIMER Timer2 is a 32-bit wake-up up/down counter timer, with a pro- grammable prescaler. The prescaler is clocked directly from one of four clock sources: namely, the core clock (which is the default selection), the low power 32.768 kHz ...
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Timer2 Control Register Name: T2CON Address: 0xFFFF0348 Default Value: 0x0000 Access: Read/write Function: This 16-bit MMR configures the mode of operation of Timer2. Table 55. T2CON MMR Bit Designations Bit Description Reserved Clock source ...
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ADuC7036 TIMER3—WATCHDOG TIMER Timer3 has two modes of operation: normal mode and watch- dog mode. The watchdog timer is used to recover from an illegal software state. When enabled, Timer3 requires periodic servicing to prevent it from forcing a reset ...
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Timer 3 Control Register Name: T3CON Address: 0xFFFF0368 Default Value: 0x0000 Access: Read/write Function: The 16-bit MMR configures the Timer3 mode of operation as described in Table 56. Table 56. T3CON MMR Bit Designations Bit Description Reserved. ...
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ADuC7036 TIMER4—STI TIMER Timer4 is a general-purpose, 16-bit up/down counter timer with a programmable prescaler. Timer4 can be clocked from the core clock or from the low power 32.768 kHz oscillator with a prescaler of 1, 16, 256, or 32,768. ...
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Table 57. T4CON MMR Bit Designations Bit Description Reserved. 17 Event select bit. Set by user to enable time capture of an event. Cleared by user to disable time capture of an event Event ...
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ADuC7036 GENERAL-PURPOSE I/O The ADuC7036 features nine general-purpose bidirectional input/ output (GPIO) pins. In general, many of the GPIO pins have multiple functions that can be configured by user code. By default, the GPIO pins are configured in GPIO mode. ...
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Table 58. External GPIO Pin to Internal Port Signal Assignments Port GPIO Pin Port Signal Port0 GPIO_0 P0.0 IRQ0 SS GPIO_1 P0.1 SCLK GPIO_2 P0.2 MISO GPIO_3 P0.3 MOSI GPIO_4 P0.4 ECLK 1 P0.5 1 P0.6 Port1 GPIO_5 P1.0 IRQ1 ...
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ADuC7036 GPIO Port0 Control Register Name: GP0CON Address: 0xFFFF0D00 Default Value: 0x11100000 Access: Read/write Function: This 32-bit MMR selects the pin function for each Port0 pin. Table 59. GP0CON MMR Bit Designations Bit Description Reserved. These bits ...
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GPIO Port1 Control Register Name: GP1CON Address: 0xFFFF0D04 Default Value: 0x10000000 Access: Read/write Function: This 32-bit MMR selects the pin function for each Port1 pin. Table 60. GP1CON MMR Bit Designations Bit Description Reserved. These bits are ...
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ADuC7036 GPIO Port2 Control Register Name: GP2CON Address: 0xFFFF0D08 Default Value: 0x01000000 Access: Read/write Function: This 32-bit MMR selects the pin function for each Port2 pin. Table 61. GP2CON MMR Bit Designations Bit Description Reserved. These bits ...
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GPIO Port0 Data Register Name: GP0DAT Address: 0xFFFF0D20 Default Value: 0x000000XX Access: Read/write Function: This 32-bit MMR configures the direction of the GPIO pins assigned to Port0 (see Table 58). This register also sets the output value for GPIO pins ...
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ADuC7036 GPIO Port1 Data Register Name: GP1DAT Address: 0xFFFF0D30 Default Value: 0x000000XX Access: Read/write Function: This 32-bit MMR configures the direction of the GPIO pins assigned to Port1 (see Table 58). This register also sets the output value for GPIO ...
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GPIO Port2 Data Register Name: GP2DAT Address: 0xFFFF0D40 Default Value: 0x000000XX Access: Read/write Function: This 32-bit MMR configures the direction of the GPIO pins assigned to Port2 (see Table 58). This register also sets the output value for GPIO pins ...
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ADuC7036 GPIO Port0 Set Register Name: GP0SET Address: 0xFFFF0D24 Access: Write only Function: This 32-bit MMR allows user code to individually bit-address external GPIO pins to set them high only. User code can accomplish this using the GP0SET MMR without ...
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GPIO Port2 Set Register Name: GP2SET Address: 0xFFFF0D44 Access: Write only Function: This 32-bit MMR allows user code to individually bit-address external GPIO pins to set them high only. User code can accomplish this using the GP2SET MMR without having ...
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ADuC7036 GPIO Port1 Clear Register Name: GP1CLR Address: 0xFFFF0D38 Access: Write only Function: This 32-bit MMR allows user code to individually bit-address external GPIO pins to clear them low only. User code can accomplish this using the GP1CLR MMR without ...
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HIGH VOLTAGE PERIPHERAL CONTROL INTERFACE The ADuC7036 integrates several high voltage circuit functions that are controlled and monitored through a registered interface consisting of two MMRs: HVCON and HVDAT. The HVCON register acts as a command byte interpreter, allowing the ...
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ADuC7036 High Voltage Interface Control Register Name: HVCON Address: 0xFFFF0804 Default Value: Updated by kernel Access: Read/write Function: This 8-bit register acts as a command byte interpreter for the high voltage control interface. Bytes written to this register are interpreted ...
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High Voltage Data Register Name: HVDAT Address: 0xFFFF080C Default Value: Updated by kernel Access: Read/write Function: This 12-bit register holds data to be written indirectly to, and read indirectly from, the following high voltage interface registers. Table 73. HVDAT MMR ...
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ADuC7036 High Voltage Configuration0 Register Name: HVCFG0 Address: Indirectly addressed via the HVCON high voltage interface Default Value: 0x00 Access: Read/write Function: This 8-bit register controls the function of high voltage circuits on the ADuC7036. This register is not an ...
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High Voltage Configuration1 Register Name: HVCFG1 Address: Indirectly addressed via the HVCON high voltage interface Default Value: 0x00 Access: Read/write Function: This 8-bit register controls the function of high voltage circuits on the ADuC7036. This register is not an MMR ...
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ADuC7036 High Voltage Monitor Register Name: HVMON Address: Indirectly addressed via the HVCON high voltage interface Default Value: 0x00 Access: Read only Function: This 8-bit, read only register reflects the current status of enabled high voltage related circuits and functions ...
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High Voltage Status Register Name: HVSTA Address: Indirectly addressed via the HVCON high voltage interface Default Value: 0x00 Access: Read only, this register should only be read on a high voltage interrupt Function: This 8-bit, read only register reflects a ...
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ADuC7036 WAKE-UP (WU) PIN The wake-up (WU) pin is a high voltage GPIO controlled through HVCON and HVDAT. Wake-Up (WU) Pin Circuit Description By default, the WU pin is configured as an output with an internal 10 kΩ pull-down resistor ...
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HANDLING INTERRUPTS FROM THE HIGH VOLTAGE PERIPHERAL CONTROL INTERFACE An interrupt controller is integrated with the high voltage circuits. If the interrupt controller is enabled through IRQEN[16], one of six high voltage sources can assert the high voltage interrupt (IRQ3) ...
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ADuC7036 UART SERIAL INTERFACE The ADuC7036 features a 16,450-compatible UART. The UART is a full-duplex, universal, asynchronous receiver/transmitter. A UART performs serial-to-parallel conversion on data characters received from a peripheral device and performs parallel-to-serial conversion on data characters received from ...
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UART REGISTER DEFINITIONS The UART interface consists of the following registers: • COMTX: 8-bit transmit register • COMRX: 8-bit receive register • COMDIV0: divisor latch (low byte) • COMDIV1: divisor latch (high byte) • COMCON0: line control register • COMCON1: ...
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ADuC7036 UART Control Register 0 Name: COMCON0 Address: 0xFFFF070C Default Value: 0x00 Access: Read/write Function: This 8-bit register controls the operation of the UART in conjunction with COMCON1. Table 81. COMCON0 MMR Bit Designations Bit Name Description 7 DLAB Divisor ...
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UART Status Register 0 Name: COMSTA0 Address: 0xFFFF0714 Default Value: 0x60 Access: Read only Function: This 8-bit, read only register reflects the current status of the UART. Table 83. COMSTA0 MMR Bit Designations Bit Name 7 6 TEMT 5 THRE ...
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ADuC7036 UART Interrupt Enable Register 0 Name: COMIEN0 Address: 0xFFFF0704 Default Value: 0x00 Access: Read/write Function: This 8-bit register enables and disables the individual UART interrupt sources. Table 84. COMIEN0 MMR Bit Designations Bit Name EDSSI ...
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UART Fractional Divider Register Name: COMDIV2 Address: 0xFFFF072C Default Value: 0x0000 Access: Read/write Function: This 16-bit register controls the operation of the fractional divider for the ADuC7036. Table 86. COMDIV2 MMR Bit Designations Bit Name 15 FBEN ...
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ADuC7036 SERIAL PERIPHERAL INTERFACE The ADuC7036 features a complete hardware serial peripheral interface (SPI) on chip. SPI is an industry-standard synchronous serial interface that allows eight bits of data to be synchronously transmitted and received simultaneously, that is, full duplex. ...
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SPI Control Register Name: SPICON Address: 0xFFFF0A10 Default Value: 0x0000 Access: Read/write Function: This 16-bit MMR configures the serial peripheral interface. Table 89. SPICON MMR Bit Designations Bit Description Reserved. 12 Continuous transfer enable. Set by the ...
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ADuC7036 SPI Status Register Name: SPISTA Address: 0xFFFF0A00 Default Value: 0x00 Access: Read only Function: This 8-bit MMR represents the current status of the serial peripheral interface. Table 90. SPISTA MMR Bit Designations Bit Description Reserved. 5 ...
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SERIAL TEST INTERFACE The ADuC7036 incorporates single-pin, serial test interface (STI) ports that can be used for end-customer evaluation or diagnostics on finished production units. The STI port transmits from one byte to six bytes of data in 12-bit packets. ...
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ADuC7036 Serial Test Interface Control Register Name: STICON Address: 0xFFFF0884 Default Value: 0x0000 Access: Read/write access, write protected by two key registers (STIKEY0 and STIKEY1). A write access to STICON is completed correctly only if the following triple write sequence ...
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Serial Test Interface Output Structure The serial test interface is a high voltage output that incorporates a low-side driver, short-circuit protection, and diagnostic pin readback capability. The output driver circuit configuration is shown in Figure 45. REF1 STI PIN READBACK ...
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ADuC7036 LIN (LOCAL INTERCONNECT NETWORK) INTERFACE The ADuC7036 features high voltage physical interfaces between the ARM7 MCU core and an external LIN bus. The LIN inter- face operates as a slave only interface, operating from 1 kBaud to 20 kBaud, ...
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LIN Hardware Synchronization Status Register Name: LHSSTA Address: 0xFFFF0780 Default Value: 0x00000000 Access: Read only Function: This LHS status register is a 32-bit register whose bits reflect the current operating status of the LIN interface. Table 92. LHSSTA MMR Bit ...
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ADuC7036 LIN Hardware Synchronization Control Register 0 Name: LHSCON0 Address: 0xFFFF0784 Default Value: 0x00000000 Access: Read/write Function: This 16-bit LHS control register, in conjunction with the LHSCON1 register, is used to configure the LIN mode of operation. Table 93. LHSCON0 ...
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Bit Description 5 Enable compare interrupt bit. Set user code to generate an LHS interrupt (IRQEN[7]) when the value in LHSVAL0 (the LIN synchronization bit timer) equals the value in the LHSCMP register. The LHS compare interrupt ...
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ADuC7036 LIN Hardware Synchronization Timer0 Register Name: LHSVAL0 Address: 0xFFFF0788 Default Value: 0x0000 Access: Read only Function: This 16-bit, read only register holds the value of the internal LIN synchronization timer. The LIN synchronization timer is clocked from an internal ...
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LIN Frame Data Transmission and Reception When the break symbol and synchronization byte have been correctly received, data is transmitted and received via the COMTX and COMRX MMRs, after UART is configured to the required baud rate. To configure the ...
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ADuC7036 Example LIN Hardware Synchronization Routine Using the following C-source code LIN initialization routine, LHSVAL1 begins to count on the first falling edge received on the LIN bus. If LHSVAL1 exceeds the value written to LHSVAL1, in this case 0x3F, ...
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LIN Diagnostics The ADuC7036 features the capability to nonintrusively monitor the current state of the LIN/BSD pin. This readback functionality is implemented using GPIO_11. The current state of the LIN/BSD pin is contained in GP2DAT[4 also possible to ...
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ADuC7036 BIT SERIAL DEVICE (BSD) INTERFACE BSD is a pulse-width-modulated signal with three possible states: sync, 0, and 1. These are detailed, along with their associated tolerances, in Table 95. The frame length is 19 bits, and commu- nication occurs ...
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BSD RELATED MMRS The ADuC7036 emulates the BSD communication protocol using a software (bit bang) interface with some hardware assis- tance form LIN hardware synchronization logic. In effect, the ADuC7036 BSD interface uses the following protocols: • An internal GPIO ...
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ADuC7036 BSD COMMUNICATION FRAME To transfer data between a master and slave, or vice versa, the construction of a BSD frame is required. A BSD frame contains seven key components: pause/sync, a direction (DIR) bit, the slave address, the register ...
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INITIALIZE BSD HARDWARE/ SOFTWARE RECEIVE SYNCHRONIZATION PULSES RECEIVE DIRECTION BIT RECEIVE SLAVE ADDRESS RECEIVE REGISTER ADDRESS RECEIVE FIRST PARITY BIT RECEIVE DATA TRANSMIT DATA FROM MASTER RECEIVE SECOND TRANSMIT SECOND PARITY BIT TRANSMIT ACK/NACK Figure 57. BSD Slave Node State ...
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ADuC7036 PART IDENTIFICATION Two registers mapped into the MMR space are intended to allow user code to identify and trace manufacturing lot ID information, part ID number, silicon mask revision, and kernel revision. This information is contained in the SYSSER0 ...
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System Serial ID Register 1 Name: SYSSER1 Address: 0xFFFF023C Default Value: 0x00000000 (updated by kernel at power-on) Access: Read/write Function: At power-on, this 32-bit register holds the values of the part ID number, silicon mask revision number, and kernel revision ...
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... Note that this MMR is also used to identify the ADuC7036 family member and prerelease silicon revision. Table 100. FEE0ADR System Identification MMR Bit Designations Bit Description Reserved ADuC703x family ID 0x2 = ADuC7032 0x3 = ADuC7033 0x4 = ADuC7034 0x6 = ADuC7036BCPZ and ADuC7036CCPZ 0x100 = ADuC7036DCPZ Others = reserved for future use Rev Page 130 of 132 ...
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SCHEMATIC This example schematic represents a basic functional circuit implementation. Additional components need to be added to ensure that the system meets any EMC and other overvoltage/overcurrent compliance requirements. VBAT IN+ SHUNT BATTERY GROUND TERMINAL REG_AVDD NTC JTAG ADAPTOR 10 ...
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... MAX 0.85 0.80 SEATING PLANE ORDERING GUIDE Temperature 1 Model Range ADuC7036BCPZ −40°C to +115°C ADuC7036BCPZ-RL −40°C to +115°C ADuC7036CCPZ −40°C to +115°C ADuC7036CCPZ-RL −40°C to +115°C ADuC7036DCPZ −40°C to +115°C ADuC7036DCPZ-RL −40°C to +115°C EVAL-ADuC7036QSPZ RoHS Compliant Part. © ...