ADUC7023BCPZ62I-RL Analog Devices Inc, ADUC7023BCPZ62I-RL Datasheet - Page 79

• Manufacturer Part Number: ADUC7023BCPZ62I-RL
• Description: Flash ARM7+8-ch,12-B ADC & 4x12-B DAC IC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7023BCPZ62I-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 44MHz
• Connectivity: I²C, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IRQP0 Register
Name:
Address:
Default value:
Access:
Table 91. IRQP0 MMR Bit Designations
Bit
31
30 to 28
27
26 to 24
23
22 to 20
19
18 to 16
15
14 to 12
11
10 to 8
7
6 to 4
3 to 0
IRQP1 Register
Name:
Address:
Default value:
Access:
Table 92. IRQP1 MMR Bit Designations
Bit
31
30 to 28
27
26 to 24
23
22 to 20
19
Name
Reserved
PLLPI
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ADCPI
FlashPI
T2PI
T1PI
T0PI
SWINTP
Name
Reserved
PSMPI
Reserved
COMPI
Reserved
IRQ0PI
Reserved
IRQP1
0xFFFF0024
0x00000000
Read and write
IRQP0
0x00000000
Read and write
0xFFFF0020
Description
Reserved bit
A priority level of 0 to 7 can be set for
PLL lock interrupt.
Reserved bit
A priority level of 0 to 7 can be set for
the ADC interrupt source.
Reserved bit
A priority level of 0 to 7 can be set for
the Flash controller interrupt source.
Reserved bit.
A priority level of 0 to 7 can be set for
Timer2.
Reserved bit.
A priority level of 0 to 7 can be set for
Timer1.
Reserved bit.
A priority level of 0 to 7 can be set for
Timer0.
Reserved bit
A priority level of 0 to 7 can be set for
the software interrupt source.
Interrupt 0 cannot be prioritized.
Description
Reserved bit.
A priority level of 0 to 7 can be set for
the power supply monitor interrupt
source.
Reserved bit.
A priority level of 0 to 7 can be set for
comparator.
Reserved bit.
A priority level of 0 to 7 can be set for
IRQ0.
Reserved bit.
Rev. B | Page 79 of 96
Bit
18 to 16
15
14 to 12
11
10 to 8
7
6 to 4
3
2 to 0
IRQP2 Register
Name:
Address:
Default value:
Access:
Table 93. IRQP2 MMR Bit Designations
Bit
31 to 23
22 to 20
19
18 to 16
15
14 to 12
11
10 to 8
7
6 to 4
3
2 to 0
Name
Reserved
PWMPI
Reserved
PLA1PI
Reserved
IRQ3PI
Reserved
IRQ2PI
Reserved
PLA0PI
Reserved
IRQ1PI
Name
SPIPI
Reserved
I2C1SPI
Reserved
I2C1MPI
Reserved
I2C0SPI
Reserved
I2C0MPI
IRQP2
0xFFFF0028
0x00000000
Read and write
Description
A priority level of 0 to 7 can be set for
SPI.
Reserved bit.
A priority level of 0 to 7 can be set for
I
Reserved bit.
A priority level of 0 to 7 can be set for
I
Reserved bits.
A priority level of 0 to 7 can be set for
I
Reserved bits.
A priority level of 0 to 7 can be set for
I
Description
Reserved bit.
A priority level of 0 to 7 can be set for
PWM.
Reserved bit.
A priority level of 0 to 7 can be set for
PLA IRQ1.
Reserved bit.
A priority level of 0 to 7 can be set for
IRQ3.
Reserved bit.
A priority level of 0 to 7 can be set for
IRQ2.
Reserved bit.
A priority level of 0 to 7 can be set for
PLA IRQ0.
Reserved bit.
A priority level of 0 to 7 can be set for
IRQ1.
2
2
2
2
C1 slave.
C1 master.
C0 slave.
C0 master.
ADuC7023