ADUC7023BCPZ62I-RL Analog Devices Inc, ADUC7023BCPZ62I-RL Datasheet - Page 69

• Manufacturer Part Number: ADUC7023BCPZ62I-RL
• Description: Flash ARM7+8-ch,12-B ADC & 4x12-B DAC IC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7023BCPZ62I-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 44MHz
• Connectivity: I²C, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 79. Feedback Configuration
Bit
10 to 9
8 to 7
PLAADC Register
Name:
Address:
Default value:
Access:
Function:
Table 80. PLAADC MMR Bit Descriptions
Bit
31 to 5
4
3 to 0
Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Value
00
01
10
11
00
01
10
11
PLAADC
0xFFFF0B48
0x00000000
Read/write
PLAADC is the PLA source for the ADC start
conversion signal.
Description
Reserved.
ADC start conversion enable bit.
This bit is set by the user to enable ADC
start conversion from PLA.
This bit is cleared by the user to disable ADC
start conversion from PLA.
ADC start conversion source.
PLA Element 0.
PLA Element 1.
PLA Element 2.
PLA Element 3.
PLA Element 4.
PLA Element 5.
PLA Element 6.
PLA Element 7.
PLA Element 8.
PLA Element 9.
PLA Element 10.
PLA Element 11.
PLA Element 12.
PLA Element 13.
PLA Element 14.
PLA Element 15.
PLAELM0
Element 15
Element 2
Element 4
Element 6
Element 1
Element 3
Element 5
Element 7
PLAELM1 to PLAELM7
Element 0
Element 2
Element 4
Element 6
Element 1
Element 3
Element 5
Element 7
Rev. B | Page 69 of 96
PLADIN Register
Name:
Address:
Default value:
Access:
Function:
Table 81. PLADIN MMR Bit Descriptions
Bit
31 to 16
15 to 0
PLADOUT Register
Name:
Address:
Default value:
Access:
Function:
Table 82. PLADOUT MMR Bit Descriptions
Bit
31 to 16
15 to 0
PLALCK Register
Name:
Address:
Default value:
Access:
Function:
PLAELM8
Element 7
Element 10
Element 12
Element 14
Element 9
Element 11
Element 13
Element 15
Description
Reserved.
Output bit from Element 15 to Element 0.
Description
Reserved.
Input bit to Element 15 to Element 0.
PLADIN
0xFFFF0B4C
0x00000000
Read/write
PLADIN is a data input MMR for PLA.
PLADOUT
0xFFFF0B50
0x00000000
Read
PLADOUT is a data output MMR for PLA.
This register is always updated.
PLALCK
0xFFFF0B54
0x00
Write
PLALCK is a PLA lock option. Bit 0 is written
only once. When set, it does not allow
modifying any of the PLA MMRs, except
PLADIN. A PLA tool is provided in the
development system to easily configure the
PLA.
PLAELM9 to PLAELM15
Element 8
Element 10
Element 12
Element 14
Element 9
Element 11
Element 13
Element 15
ADuC7023