ADUC7023BCPZ62I-RL Analog Devices Inc, ADUC7023BCPZ62I-RL Datasheet - Page 46

• Manufacturer Part Number: ADUC7023BCPZ62I-RL
• Description: Flash ARM7+8-ch,12-B ADC & 4x12-B DAC IC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7023BCPZ62I-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 44MHz
• Connectivity: I²C, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7023
Comparator Interface
The comparator interface consists of a 16-bit MMR, CMPCON, which is described in Table 45.
CMPCON Register
Name:
Address:
Default value:
Access:
Table 45. CMPCON MMR Bit Descriptions
Bit
15 to 11
10
9 to 8
7 to 6
5
4 to 3
2
1
0
Value
00
01
10
11
00
01
10
11
00
11
01/10
Name
CMPEN
CMPIN
CMPOC
CMPOL
CMPRES
CMPHYST
CMPORI
CMPOFI
CMPCON
0xFFFF0444
0x0000
Read/write
Description
Reserved.
Comparator enable bit.
This bit is set by the user to enable the comparator.
This bit is cleared by the user to disable the comparator.
Comparator negative input select bits.
AV
ADC3 input.
DAC0 output.
Reserved.
Comparator output configuration bits.
Reserved.
Reserved.
Output on COMP
IRQ.
Comparator output logic state bit. When low, the comparator output is high if the positive input (CMP0)
is above the negative input (CMP1). When high, the comparator output is high if the positive input is
below the negative input.
Response time.
5 μs response time typical for large signals (2.5 V differential).
17 μs response time typical for small signals (0.65 mV differential).
3 μs typical.
Reserved.
Comparator hysteresis bit.
This bit is set by the user to have a hysteresis of about 7.5 mV.
This bit is cleared by the user to have no hysteresis.
Comparator output rising edge interrupt.
This bit is set automatically when a rising edge occurs on the monitored voltage (CMP0).
This bit is cleared by the user by writing a 1 to this bit.
Comparator output rallying edge interrupt.
This bit is set automatically when a falling edge occurs on the monitored voltage (CMP0).
This bit is cleared by user.
DD
/2.
OUT
.
Rev. B | Page 46 of 96