ADUC7023BCPZ62I-RL Analog Devices Inc, ADUC7023BCPZ62I-RL Datasheet - Page 16

• Manufacturer Part Number: ADUC7023BCPZ62I-RL
• Description: Flash ARM7+8-ch,12-B ADC & 4x12-B DAC IC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7023BCPZ62I-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 44MHz
• Connectivity: I²C, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b, D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7023
40-LFCSP
9
10
11
12
21
22
16
15
29
7
34
33
14
13
35
40
1
Pin No.
32-LFCSP
7
8
9
10
17
18
N/A
N/A
N/A
N/A
26
25
12
11
27
32
1
Mnemonic
P0.4/IRQ0/SCL0/PLAI[0]/CONV
P0.5/SDA0/PLAI[1]/COMP
P0.6/MISO/SCL1/PLAI[2]
P0.7/MOSI/SDA1/PLAO[0]
XCLKI
XCLKO
P1.7/PWM3/SDA1/PLAI[6]
P1.6/PWM2/SCL1/PLAI[5]
P1.5/ADC6/PWM
P1.4/ADC10/PLAO[3]
P1.3/ADC5/IRQ3/PLAI[4]
P1.2/ADC4/IRQ2/PLAI[3]/ECLK/
P1.1/SS/IRQ1/PWM1/PLAO[2]/T1
P1.0/SPICLK/PWM0/PLAO[1]
V
AGND
AV
REF
DD
TRIPINPUT
/PLAO[4]
OUT
Rev. B | Page 16 of 96
Description
General-Purpose Input and Output Port 0.4/External Interrupt Request
0//I
External Convert Start. By default, this pin is configured as a digital input
with a weak pull-up resistor enabled.
General-Purpose Input and Output Port 0.5/I
Logic Array Input Element 1/Voltage Comparator Output. By default, this
pin is configured as a digital input with a weak pull-up resistor enabled.
General-Purpose Input and Output Port 0.6/SPI MISO Signal/I
32-Lead Package/Programmable Logic Array Input Element 2. By default,
this pin is configured as a digital input with a weak pull-up resistor
enabled.
General-Purpose Input and Output Port 0.7/SPI MOSI Signal/I
Signal On 32-Lead Package/Programmable Logic Array Output Element 0.
By default, this pin is configured as a digital input with a weak pull-up
resistor enabled.
Input to the Crystal Oscillator Inverter and Input to the Internal Clock
Generator Circuits. Connect to DGND if unused.
Output from the Crystal Oscillator Inverter. Leave unconnected if unused.
General-Purpose Input and Output Port 1.7/PWM Output 3/I
Signal/Programmable Logic Array Input Element 6. By default, this pin is
configured as a digital input with a weak pull-up resistor enabled.
General-Purpose Input and Output Port 1.6/PWM Output 2/I
Signal/Programmable Logic Array Input Element 5. By default, this pin is
configured as a digital input with a weak pull-up resistor enabled.
General-Purpose Input and Output Port 1.5/ADC Single-Ended or
Differential Analog Input 6/PWM
Element 4. By default, this pin is configured as a digital input with a weak
pull-up resistor enabled. When used as ADC input, the pull-up resistor
should be disabled manually.
General-Purpose Input and Output Port 1.4/ADC Single-Ended or
Differential Analog Input 10/Programmable Logic Array Output Element 3.
By default, this pin is configured as a digital input with a weak pull-up
resistor enabled. When used as ADC input, the pull-up resistor should be
disabled manually.
General-Purpose Input and Output Port 1.3/ADC Single-Ended or
Differential Analog Input 5/External Interrupt Request 3/Programmable
Logic Array Input Element 4.
By default, this pin is configured as a digital input with a weak pull-up
resistor enabled. When used as ADC input, the pull-up resistor should be
disabled manually.
General-Purpose Input and Output Port 1.2/ADC Single-Ended or
Differential Analog Input 4/External Interrupt Request 2/Programmable
Logic Array Input Element 3/Input-Output for External Clock.
By default, this pin is configured as a digital input with a weak pull-up
resistor enabled. When used as ADC input, the pull-up resistor should be
disabled manually.
General-Purpose Input and Output Port 1.1/SPI Interface Slave Select
(Active Low)/External Interrupt Request 1/PWM Output 1/Programmable
Logic Array Output Element 2/Timer 1 Input Clock. By default, this pin is
configured as a digital input with a weak pull-up resistor enabled.
General-Purpose Input and Output Port 1.0/SPI Interface Clock Signal/
PWM Output 0/Programmable Logic Array Output Element 1. By default,
this pin is configured as a digital input with a weak pull-up resistor
enabled.
2.5 V Internal Voltage Reference. Must be connected to a 0.47 μF capacitor
when using the internal reference.
Analog Ground. Ground reference point for the analog circuitry.
3.3 V Analog Power.
2
C0 Clock Signal/Programmable Logic Array Input Element 0/ADC
TRIPINPUT
/Programmable Logic Array Output
2
C0 Data Signal/Programmable
2
2
2
2
C1 Clock On
C1 Data
C Data
C Clock