ADT7470ARQZ-REEL Analog Devices Inc, ADT7470ARQZ-REEL Datasheet - Page 4

• Manufacturer Part Number: ADT7470ARQZ-REEL
• Description: IC,Motor Controller,SSOP,16PIN
• Manufacturer: Analog Devices Inc

Specifications of ADT7470ARQZ-REEL

• Function: Fan Control, Temp Monitor
• Topology: ADC, Comparator, Fan Speed Control, Register Bank
• Sensor Type: External
• Sensing Temperature: External Sensor
• Output Type: I²C™
• Output Alarm: No
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADT7470EBZ - BOARD EVALUATION FOR ADT7470
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADT7470
SERIAL BUS TIMING SPECIFICATIONS
Table 2.
Parameter
SERIAL BUS TIMING
1
2
3
4
5
Typical values are at %A = 25°C and represent the most likely parametric norm.
Logic inputs accept input high voltages up to 5 V even when the device is operating at supply voltages below 5 V.
VDD should never be floated in the presence of SCL/SDA activity. Charge injection can be sufficient to induce approximately 0.6 V on VDD.
All voltages are measured with respect to GND, unless otherwise specified.
Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V for a rising edge.
Clock Frequency, f
Glitch Immunity, t
Bus Free Time, t
Start Setup Time, t
Start Hold Time, t
SCL Low Time, t
SCL High Time, t
SCL, SDA Rise Time, t
SCL, SDA Fall Time, t
Data Setup Time, t
Detect Clock Low Timeout, t
SDA
SCL
1, 2, 3, 4, 5
P
BUF
LOW
t
HIGH
BUF
HD;STA
SW
SCLK
SU;DAT
SU;STA
S
f
r
t
HD;STA
TIMEOUT
t
LOW
t
R
t
HD;DAT
t
Figure 2. Serial Bus Timing Diagram
HIGH
t
F
t
SU;DAT
Rev. C | Page 4 of 40
Min
1.3
600
600
1.3
0.6
100
25
Typ
50
28
S
Max
400
300
300
31
t
SU;STA
t
HD;STA
Unit
kHz
ns
μs
ns
ns
μs
μs
ns
ns
ns
ms
Test Conditions/Comments
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
Can be optionally disabled,
via Configuration Register 1
(see Table 6)
t
SU;STO
P