ADT7470ARQZ-REEL Analog Devices Inc, ADT7470ARQZ-REEL Datasheet - Page 18

• Manufacturer Part Number: ADT7470ARQZ-REEL
• Description: IC,Motor Controller,SSOP,16PIN
• Manufacturer: Analog Devices Inc

Specifications of ADT7470ARQZ-REEL

• Function: Fan Control, Temp Monitor
• Topology: ADC, Comparator, Fan Speed Control, Register Bank
• Sensor Type: External
• Sensing Temperature: External Sensor
• Output Type: I²C™
• Output Alarm: No
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADT7470EBZ - BOARD EVALUATION FOR ADT7470
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADT7470
SMBALERT INTERRUPT
The ADT7470 can be polled for status, or an SMBALERT
interrupt can be generated for out-of-limit conditions. Note
how the SMBALERT output and status bits behave when
writing interrupt handler software.
Figure 15 shows how the SMBALERT output and sticky status
bits behave. Once a limit is exceeded, the corresponding status
bit is set to 1. The status bit remains set until the error condition
subsides the status register is read. The status bits are referred
to as sticky because they remain set until read by software. This
ensures that an out-of-limit event cannot be missed if software
is polling the device periodically. The SMBALERT output
remains low for the duration that a reading is out of limit until
the status register is read. This has implications for how
software handles the interrupt.
TEMPERATURE
TEMPERATURE
SMBALERT
HIGH LIMIT
"STICKY"
SMBALERT
HIGH LIMIT
STATUS
"STICKY"
STATUS
BIT
Figure 16. How Masking the Interrupt Source Affects SMBALERT Output
BIT
Figure 15. SMBALERT and Status Bit Behavior
Rev. C | Page 18 of 40
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
INTERRUPT
MASK BIT SET
Handling SMBALERT Interrupts
To prevent the system from being tied up servicing interrupts,
handle the SMBALERT interrupt as follows:
1.
2.
3.
4.
5.
6.
7.
Detect the SMBALERT assertion.
Enter the interrupt handler.
Read the status registers to identify the interrupt source.
Mask the interrupt source by setting the appropriate mask
bit in the interrupt mask registers (Register 0x72 and
Register 0x73).
Take the appropriate action for a given interrupt source.
Exit the interrupt handler.
Periodically poll the status registers. If the interrupt status
bit is cleared, reset the corresponding interrupt mask bit
to 0. This causes the SMBALERT output and status bits
to behave as shown in
(SMBALERT RE-ENABLED)
INTERRUPT MASK BIT
(TEMP BELOW LIMIT)
CLEARED ON READ
CLEARED ON READ
(TEMP BELOW LIMIT)
CLEARED
Figure 16
.