ADSP-BF514BBCZ-4F4 Analog Devices Inc, ADSP-BF514BBCZ-4F4 Datasheet - Page 42

• Manufacturer Part Number: ADSP-BF514BBCZ-4F4
• Description: Low-Pwr BF Proc W/flash & Cnsmr Conctvty
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF514BBCZ-4F4

• Interface: I²C, PPI, RSI, SPI, SPORT, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: FLASH (4Mbit)
• On-chip Ram: 116kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.30V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 168-LFBGA
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Device Input Clock Speed: 400MHz
• Ram Size: 48KB
• Program Memory Size: 1024KB
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Package: 168CSP-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 400 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Serial Ports
Table 36
through
Table 36. Serial Ports—External Clock
1
2
3
Table 37. Serial Ports—Internal Clock
1
2
Parameter
Timing Requirements
t
t
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
Parameter
Timing Requirements
t
t
t
t
Switching Characteristics
t
t
t
t
t
Referenced to sample edge.
Verified in design but untested.
Referenced to drive edge.
Referenced to sample edge.
Referenced to drive edge.
SFSE
HFSE
SDRE
HDRE
SCLKEW
SCLKE
SUDTE
SUDRE
DFSE
HOFSE
DDTE
HDTE
SFSI
HFSI
SDRI
HDRI
DFSI
HOFSI
DDTI
HDTI
SCLKIW
Figure 24 on Page 45
through
TFSx/RFSx Setup Before TSCLKx/RSCLKx
TFSx/RFSx Hold After TSCLKx/RSCLKx
Receive Data Setup Before RSCLKx
Receive Data Hold After RSCLKx
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated
TFSx/RFSx)
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated
TFSx/RFSx)
Transmit Data Delay After TSCLKx
Transmit Data Hold After TSCLKx
TSCLKx/RSCLKx Width
TFSx/RFSx Setup Before TSCLKx/RSCLKx
TFSx/RFSx Hold After TSCLKx/RSCLKx
Receive Data Setup Before RSCLKx
Receive Data Hold After RSCLKx
TSCLKx/RSCLKx Width
TSCLKx/RSCLKx Period
Start-Up Delay From SPORT Enable To First External TFSx
Start-Up Delay From SPORT Enable To First External RFSx
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated
TFSx/RFSx)
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated
TFSx/RFSx)
Transmit Data Delay After TSCLKx
Transmit Data Hold After TSCLKx
Table 39 on Page 45
2
2
3
3
describe serial port operations.
and
Figure 21 on Page 43
1
1
2
3
2
3
1
1
1
1
Rev. A | Page 42 of 72 | August 2010
1
1
2
2
Min
11
–1.5
11
–1.5
−2
−1.8
10
Min
3
3
3
3.5
7
2 × t
4 × t
4 × t
0
0
SCLK
SCLKE
SCLKE
1.8V Nominal
1.8V Nominal
V
V
DDMEM
DDMEM
Max
3
3
Max
10
10
Min
9.6
–1.5
9.6
–1.5
−1
−1.5
8
Min
3
3
3
3
4.5
2 × t
4 × t
4 × t
0
0
SCLK
SCLKE
SCLKE
2.5/3.3V Nominal
2.5/3.3V Nominal
V
V
DDMEM
DDMEM
Max
3
3
Max
10
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns