ADSP-BF514BBCZ-4F4 Analog Devices Inc, ADSP-BF514BBCZ-4F4 Datasheet - Page 10

• Manufacturer Part Number: ADSP-BF514BBCZ-4F4
• Description: Low-Pwr BF Proc W/flash & Cnsmr Conctvty
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF514BBCZ-4F4

• Interface: I²C, PPI, RSI, SPI, SPORT, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: FLASH (4Mbit)
• On-chip Ram: 116kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.30V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 168-LFBGA
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Device Input Clock Speed: 400MHz
• Ram Size: 48KB
• Program Memory Size: 1024KB
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Package: 168CSP-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 400 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Table 4. Peripheral Interrupt Assignment (Continued)
Event Control
The ADSP-BF51x processors provide a very flexible mechanism
to control the processing of events. In the CEC, three registers
are used to coordinate and control events. Each register is 16
bits wide.
The SIC allows further control of event processing by providing
three pairs of 32-bit interrupt control and status registers. Each
register contains a bit corresponding to each of the peripheral
interrupt events shown in
Peripheral Interrupt Event
PWM Trip Interrupt
PWM Sync Interrupt
PTP Status Interrupt
• CEC interrupt latch register (ILAT)—Indicates when
• CEC interrupt mask register (IMASK)—Controls the
• CEC interrupt pending register (IPEND)—The IPEND
• SIC interrupt mask registers (SIC_IMASKx)—Control the
• SIC interrupt status registers (SIC_ISRx)—As multiple
• SIC interrupt wakeup enable registers (SIC_IWRx)—By
events have been latched. The appropriate bit is set when
the processor has latched the event and cleared when the
event has been accepted into the system. This register is
updated automatically by the controller, but it may be writ-
ten only when its corresponding IMASK bit is cleared.
masking and unmasking of individual events. When a bit is
set in the IMASK register, that event is unmasked and is
processed by the CEC when asserted. A cleared bit in the
IMASK register masks the event, preventing the processor
from servicing the event even though the event may be
latched in the ILAT register. This register may be read or
written while in supervisor mode. (Note that general-
purpose interrupts can be globally enabled and disabled
with the STI and CLI instructions, respectively.)
register keeps track of all nested events. A set bit in the
IPEND register indicates the event is currently active or
nested at some level. This register is updated automatically
by the controller but may be read while in supervisor mode.
masking and unmasking of each peripheral interrupt event.
When a bit is set in these registers, that peripheral event is
unmasked and is processed by the system when asserted. A
cleared bit in the register masks the peripheral event, pre-
venting the processor from servicing the event.
peripherals can be mapped to a single event, these registers
allow the software to determine which peripheral event
source triggered the interrupt. A set bit indicates the
peripheral is asserting the interrupt, and a cleared bit indi-
cates the peripheral is not asserting the event.
enabling the corresponding bit in these registers, a periph-
eral can be configured to wake up the processor, should the
core be idled when the event is generated. For more infor-
mation see
Dynamic Power Management on Page
Table 4 on Page
8.
General Purpose
Interrupt (at Reset)
IVG10
IVG10
IVG10
Rev. A | Page 10 of 72 | August 2010
15.
Peripheral
Interrupt ID
53
54
55
Because multiple interrupt sources can map to a single general-
purpose interrupt, multiple pulse assertions can occur simulta-
neously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND reg-
ister contents are monitored by the SIC as the interrupt
acknowledgement.
The appropriate ILAT register bit is set when an interrupt rising
edge is detected (detection requires two core clock cycles). The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the proces-
sor pipeline. At this point the CEC recognizes and queues the
next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the general-
purpose interrupt to the IPEND output asserted is three core
clock cycles; however, the latency can be much higher, depend-
ing on the activity within and the state of the processor.
DMA CONTROLLERS
The ADSP-BF51x processors have multiple independent DMA
channels that support automated data transfers with minimal
overhead for the processor core. DMA transfers can occur
between the processor's internal memories and any of its DMA-
capable peripherals. Additionally, DMA transfers can be accom-
plished between any of the DMA-capable peripherals and
external devices connected to the external memory interfaces,
including the SDRAM controller and the asynchronous mem-
ory controller. DMA-capable peripherals include the Ethernet
MAC, RSI, SPORTs, SPIs, UARTs, and PPI. Each individual
DMA-capable peripheral has at least one dedicated DMA
channel.
The processors’ DMA controller supports both one-dimen-
sional (1-D) and two-dimensional (2-D) DMA transfers. DMA
transfer initialization can be implemented from registers or
from sets of parameters called descriptor blocks.
The 2-D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to ±32K elements. Furthermore, the
column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be de-
interleaved on the fly.
Examples of DMA types supported by the DMA controller
include:
• A single, linear buffer that stops upon completion
• A circular, auto-refreshing buffer that interrupts on each
full or fractionally full buffer
Default Core
Interrupt ID
3
3
3
SIC Registers
IAR6
IAR6
IAR6
IMASK1 and ISR1
IMASK1 and ISR1
IMASK1 and ISR1