ADSP-BF514BBCZ-4F4 Analog Devices Inc, ADSP-BF514BBCZ-4F4 Datasheet - Page 32

• Manufacturer Part Number: ADSP-BF514BBCZ-4F4
• Description: Low-Pwr BF Proc W/flash & Cnsmr Conctvty
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF514BBCZ-4F4

• Interface: I²C, PPI, RSI, SPI, SPORT, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: FLASH (4Mbit)
• On-chip Ram: 116kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.30V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 168-LFBGA
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Device Input Clock Speed: 400MHz
• Ram Size: 48KB
• Program Memory Size: 1024KB
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Package: 168CSP-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 400 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
TIMING SPECIFICATIONS
Clock and Reset Timing
Table 26
Absolute Maximum Ratings on Page
CLKIN and clock multipliers must not select core/peripheral
clocks in excess of 400 MHz/100 MHz.
Table 26. Clock and Reset Timing
1
2
3
4
5
Table 27. Power-Up Reset Timing
Parameter
Timing Requirements
t
Parameter
Timing Requirements
f
t
t
t
Switching Characteristic
t
Applies to PLL bypass mode and PLL nonbypass mode.
Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed f
The t
If the DF bit in the PLL_CTL register is set, the minimum f
Applies after power-up sequence is complete. See
RST_IN_PWR
CKIN
CKINL
CKINH
WRST
BUFDLAY
Table 13 on Page
CKIN
period (see
V
and
DD_SUPPLIES
CLKIN
RESET Deasserted after the V
Stable and Within Specification
Figure 8
26.
CLKBUF
Figure
CLKIN
CLKIN Frequency
CLKIN Low Pulse
CLKIN High Pulse
RESET Asserted Pulse Width Low
CLKIN to CLKBUF Delay
describe clock and reset operations. Per
8) equals 1/f
t
CKINL
CKIN
1
.
1, 2, 3, 4
1
30, combinations of
t
CKIN
Table 27
DDINT
t
CKINH
, V
DDEXT
CKIN
and
, V
specification is 24 MHz for commercial/industrial models and 28 MHz for automotive models.
Rev. A | Page 32 of 72 | August 2010
Figure 9
DDRTC
5
t
RST_IN_PWR
, V
Figure 8. Clock and Reset Timing
Figure 9. Power-Up Reset Timing
t
WRST
DDMEM
for power-up reset timing.
, V
DDOTP
, and CLKIN Pins are
Min
12
10
10
11 × t
VCO
CKIN
t
, f
NOBOOT
CCLK
t
BUFDLAY
, and f
Min
3500 × t
SCLK
settings discussed in
CKIN
Max
50
11
Table 12 on Page 26
Max
t
BUFDLAY
through
Unit
ns
MHz
ns
ns
ns
Unit
ns