ADSP-BF504BCPZ-3F Analog Devices Inc, ADSP-BF504BCPZ-3F Datasheet - Page 65

• Manufacturer Part Number: ADSP-BF504BCPZ-3F
• Description: Blackfin W/Processor & Executable Flash
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF504BCPZ-3F

• Interface: CAN, EBI/EMI, I²C, IrDA, PPI, SPI, SPORT, UART/USART
• Clock Rate: 300MHz
• Non-volatile Memory: FLASH (16MB)
• On-chip Ram: 68kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.29V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

to make use of the full dynamic range of the part. A dc input is
applied to the V
vides an offset from ground or a pseudo ground for the V
input. The benefit of pseudo differential inputs is that they sepa-
rate the analog input signal ground from the ADC’s ground
allowing dc common-mode voltages to be cancelled.
The typical voltage range for the V
ferential mode, is shown in
vs. V
Figure 75 (V
ential Mode with V
Mode Connection
pseudo differential mode.
GND
Figure 73. Dual Op Amp Circuit to Convert a Single-Ended Bipolar Signal
REF
–0.2
–0.4
in Pseudo Differential Mode with V
1.0
0.8
0.6
0.4
0.2
2 × V
0
0
IN–
REF
Figure 74. V
Pseudo Differential Mode with V
220kŸ
Input Voltage Range vs. V
IN–
p–p
440Ÿ
20kŸ
0.5
into a Differential Unipolar Signal
A
Diagram) shows a connection diagram for
pin. The voltage applied to this input pro-
DD
= 5
IN-
220Ÿ
220Ÿ
220Ÿ
Input Voltage Range vs. V
1.0
V).
Figure 74 (V
V+
V–
V+
V–
Figure 76 (Pseudo Differential
1
10kŸ
ADDITIONAL PINS OMITTED FOR CLARITY.
V
REF
27Ÿ
27Ÿ
1.5
IN–
(V)
pin, while in pseudo dif-
IN–
2.0
REF
DD
Input Voltage Range
DD
= 3 V
3.75V
2.5V
1.25V
3.75V
2.5V
1.25V
in Pseudo Differ-
= 3
REF
in
2.5
Rev. 0 | Page 65 of 80 | December 2010
V) and
T
V
V
A
IN+
IN–
= 25°C
(D
CAP
ADC
IN+
3.0
V
A/D
REF
1
0.47μF
CAP
B)
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
Analog Input Selection
The analog inputs of the ADC can be configured as single-
ended or true differential via the SGL/DIFF logic pin, as shown
in
tion). If this pin is tied to a logic low, the analog input channels
to each on-chip ADC are set up as three true differential pairs. If
this pin is at logic high, the analog input channels to each on-
chip ADC are set up as six single-ended analog inputs. The
required logic level on this pin needs to be established prior to
the acquisition time and remain unchanged during the conver-
sion time until the track-and-hold has returned to track. The
track-and-hold returns to track on the 13
ADSCLK after the CS falling edge (see
face Timing
be recognized by the ADC; therefore, it is necessary to keep the
same logic level during acquisition and conversion to avoid cor-
rupting the conversion in progress.
For example, in
Ended
the duration of both the acquisition and conversion times so the
analog inputs are configured as single ended for that conversion
(Sampling Point A). The logic level of the SGL/DIFF changed to
low after the track-and-hold returned to track and prior to the
Figure 77 (Selecting Differential or Single-Ended Configura-
Configuration) the SGL/DIFF pin is set at logic high for
–0.5
Figure 76. Pseudo Differential Mode Connection Diagram
V
2.5
2.0
1.5
1.0
0.5
p–p
REF
0
0
T
Diagram)). If the level on this pin is changed, it will
A
Figure 75. V
= 25°C
0.5
Pseudo Differential Mode with V
Figure 77 (Selecting Differential or Single-
1.0
1
ADDITIONAL PINS OMITTED FOR CLARITY.
IN–
1.5
DC INPUT
VOLTAGE
Input Voltage Range vs. V
2.0
V
REF
2.5
(V)
3.0
Figure 87 (Serial Inter-
V
V
th
IN+
IN–
V
DD
REF (
rising edge of
3.5
= 5 V
0.47μF
D
ADC
REF
CAP
4.0
in
A/D
1
CAP
4.5
B)
5.0