ADSP-BF504BCPZ-3F Analog Devices Inc, ADSP-BF504BCPZ-3F Datasheet - Page 21

• Manufacturer Part Number: ADSP-BF504BCPZ-3F
• Description: Blackfin W/Processor & Executable Flash
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF504BCPZ-3F

• Interface: CAN, EBI/EMI, I²C, IrDA, PPI, SPI, SPORT, UART/USART
• Clock Rate: 300MHz
• Non-volatile Memory: FLASH (16MB)
• On-chip Ram: 68kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.29V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SIGNAL DESCRIPTIONS
Signal definitions for the ADSP-BF50x processors are listed in
Table
are listed in
In order to maintain maximum function and reduce package
size and pin count, some pins have multiple, multiplexed func-
tions. In cases where pin function is reconfigurable, the default
state is shown in plain text, while the alternate functions are
shown in italics.
During and immediately after reset, all processor signals (not
ADC signals) are three-stated with the following exceptions:
EXT_WAKE is driven high and XTAL is driven in conjunction
with CLKIN to create a crystal oscillator circuit. During
Table 11. Processor—Signal Descriptions
Signal Name
Port F: GPIO and Multiplexed Peripherals
Port G: GPIO and Multiplexed Peripherals
PF0/TSCLK0/UA0_RX/TMR6/CUD0
PF1/RSCLK0/UA0_TX/TMR5/CDG0
PF2/DT0PRI/PWM0_BH/PPI_D8/CZM0
PF3/TFS0/PWM0_BL/PPI_D9/CDG0
PF4/RFS0/PWM0_CH/PPI_D10/TACLK0
PF5/DR0PRI/PWM0_CL/PPI_D11/TACLK1
PF6/UA1_TX/PWM0_TRIP/PPI_D12
PF7/UA1_RX/PWM0_SYNC/PPI_D13/TACI3
PF8/UA1_RTS/DT0SEC/PPI_D7
PF9/UA1_CTS/DR0SEC/PPI_D6/CZM0
PF10/SPI0_SCK/TMR2/PPI_D5
PF11/SPI0_MISO/PWM0_TRIP/PPI_D4/TACLK2
PF12/SPI0_MOSI/PWM0_SYNC/PPI_D3
PF13/SPI0_SEL1/TMR3/PPI_D2/SPI0_SS
PF14/SPI0_SEL2/PWM0_AH/PPI_D1
PF15/SPI0_SEL3/PWM0_AL/PPI_D0
PG0/SPI1_SEL3/TMRCLK/PPI_CLK/UA1_RX/TACI4 I/O GPIO/SPI1 Slave Select 3/Timer CLK/PPI Clock/UART1 RX/Alt Capture In 4
PG1/SPI1_SEL2/PPI_FS3/CAN_RX/TACI5
PG2/SPI1_SEL1/TMR4/CAN_TX/SPI1_SS
PG3/HWAIT/SPI1_SCK/DT1SEC/UA1_TX
PG4/SPI1_MOSI/DR1SEC/PWM1_SYNC/TACLK6
PG5/SPI1_MISO/TMR7/PWM1_TRIP
PG6/ACM_SGLDIFF/SD_D3/PWM1_AH
PG7/ACM_RANGE/SD_D2/PWM1_AL
PG8/DR1SEC/SD_D1/PWM1_BH
PG9/DR1PRI/SD_D0/PWM1_BL
PG10/RFS1/SD_CMD/PWM1_CH/TACI6
PG11/RSCLK1/SD_CLK/PWM1_CL/TACLK7
PG12/UA0_RX/SD_D4/PPI_D15/TACI2
PG13/UA0_TX/SD_D5/PPI_D14/CZM1
11. All pins for the ADC (ADSP-BF506F processor only)
Table
12.
Type Function
Rev. 0 | Page 21 of 80 | December 2010
I/O GPIO/SPORT0 TX Serial CLK/UART0 RX/Timer6/Count Up Dir 0
I/O GPIO/SPORT0 RX Serial CLK/UART0 TX/Timer5/Count Down Dir 0
I/O GPIO/SPORT0 TX Pri Data/PWM0 Drive B Hi/PPI Data 8/Counter Zero Marker 0
I/O GPIO/SPORT0 TX Frame Sync/PWM0 Drive B Lo/PPI Data 9/Count Down Dir 0
I/O GPIO/SPORT0 RX Frame Sync/PWM0 Drive C Hi/PPI Data 10/Alt Timer CLK 0
I/O GPIO/SPORT0 Pri RX Data/PWM0 Drive C Lo/PPI Data 11/Alt Timer CLK 1
I/O GPIO/UART1 TX/PWM0 TRIP/PPI Data 12
I/O GPIO/UART1 RX/PWM0 SYNC/PPI Data 13/Alt Capture In 3
I/O GPIO/UART1 RTS/SPORT0 TX Sec Data/PPI Data 7
I/O GPIO/UART1 CTS/SPORT0 Sec RX Data/PPI Data 6/Counter Zero Marker 0
I/O GPIO/SPI0 SCK/Timer2/PPI Data 5
I/O GPIO/SPI0 MISO/PWM0 TRIP/PPI Data 4/Alt Timer CLK 2
I/O GPIO/SPI0 MOSI/PWM0 SYNC/PPI Data 3
I/O GPIO/SPI0 Slave Select 1/Timer3/PPI Data 2/SPI0 Slave Select In
I/O GPIO/SPI0 Slave Select 2/PWM0 AH/PPI Data 1
I/O GPIO/SPI0 Slave Select 3/PWM0 AL/PPI Data 0
I/O GPIO/SPI1 Slave Select 2/PPI FS3/CAN RX/Alt Capture In 5
I/O GPIO/SPI1 Slave Select 1/Timer4/CAN TX/SPI1 Slave Select In
I/O GPIO/HWAIT/SPI1 SCK/SPORT1 TX Sec Data/UART1 TX
I/O GPIO/SPI1 MOSI/SPORT1 Sec RX Data/PWM1 SYNC/Alt Timer CLK 6
I/O GPIO/SPI1 MISO/Timer7/PWM1 TRIP
I/O GPIO/ADC CM SGL DIFF/SD Data 3/PWM1 Drive A Hi
I/O GPIO/ADC CM RANGE/SD Data 2/PWM1 Drive A Lo
I/O GPIO/SPORT1 Sec RX Data/SD Data 1/PWM1 Drive B Hi
I/O GPIO/SPORT1 Pri RX Data/SD Data 0/PWM1 Drive B Lo
I/O GPIO/SPORT1 RX Frame Sync/SD CMD/PWM1 Drive C Hi/Alt Capture In 6
I/O GPIO/SPORT1 RX Serial CLK/SD CLK/PWM1 Drive C Lo/Alt Timer CLK 7
I/O GPIO/UART0 RX/SD Data 4/PPI Data 15/Alt Capture In 2
I/O GPIO/UART0 TX/SD Data 5/PPI Data 14/Counter Zero Marker 1
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
hibernate, all signals are three-stated with the following excep-
tions: EXT_WAKE is driven low and XTAL is driven to a solid
logic level.
During and immediately after reset, all I/O pins have their input
buffers disabled until enabled by user software with the excep-
tion of the pins that need pull-ups or pull-downs, as noted in
Table
Adding a parallel termination to CLKOUT may prove useful in
further enhancing signal integrity. Be sure to verify over-
shoot/undershoot and signal integrity specifications on actual
hardware.
11.
Driver
Type
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C