ADSP-BF504BCPZ-3F Analog Devices Inc, ADSP-BF504BCPZ-3F Datasheet - Page 34

• Manufacturer Part Number: ADSP-BF504BCPZ-3F
• Description: Blackfin W/Processor & Executable Flash
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF504BCPZ-3F

• Interface: CAN, EBI/EMI, I²C, IrDA, PPI, SPI, SPORT, UART/USART
• Clock Rate: 300MHz
• Non-volatile Memory: FLASH (16MB)
• On-chip Ram: 68kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.29V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Rohs Compliant: YES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF504/ADSP-BF504F/ADSP-BF506F
Parallel Peripheral Interface Timing
Table 27
Figure 22 on Page 40
operations.
Table 27. Parallel Peripheral Interface Timing
1
2
Parameter
Timing Requirements
t
t
Timing Requirements—GP Input and Frame Capture Modes
t
t
t
t
t
Switching Characteristics—GP Output and Frame Capture Modes
t
t
t
t
PPI_CLK frequency cannot exceed f
The PPI port is fully enabled 4 PPI clock cycles after the PAB write to the PPI port enable bit. Only after the PPI port is fully enabled are external frame syncs and data words
PCLKW
PCLK
PSUD
SFSPE
HFSPE
SDRPE
HDRPE
DFSPE
HOFSPE
DDTPE
HDTPE
guaranteed to be received correctly by the PPI peripheral.
and
Figure 14 on Page
PPI_CLK Width
PPI_CLK Period
External Frame Sync Startup Delay
External Frame Sync Setup Before PPI_CLK
(Nonsampling Edge for Rx, Sampling Edge for Tx)
External Frame Sync Hold After PPI_CLK
Receive Data Setup Before PPI_CLK
Receive Data Hold After PPI_CLK
Internal Frame Sync Delay After PPI_CLK
Internal Frame Sync Hold After PPI_CLK
Transmit Data Delay After PPI_CLK
Transmit Data Hold After PPI_CLK
PPI_FS1/2
PPI_FS1/2
PPI_DATA
PPI_CLK
PPI_CLK
describe parallel peripheral interface
1
SCLK
1
34,
/2
t
SFSPE
Figure 20 on Page
FRAME SYNC SAMPLED
DATA SAMPLED /
Figure 14. PPI GP Rx Mode with External Frame Sync Timing
2
Figure 13. PPI with External Frame Sync Timing
Rev. 0 | Page 34 of 80 | December 2010
39, and
t
HFSPE
t
SDRPE
FRAME SYNC SAMPLED
t
DATA SAMPLED /
PSUD
Min
t
2 × t
4 × t
6.7
1.5
4.1
2
1.7
2.3
SCLK
–1.5
SCLK
PCLK
t
PCLKW
V
–1.5
DDEXT
t
HDRPE
= 1.8 V
Max
8.7
8.7
t
PCLK
Min
t
2 × t
4 × t
6.7
1.5
3.5
1.6
1.7
1.9
SCLK
–1.5
V
SCLK
PCLK
DDEXT
–1.5
= 2.5 V/3.3 V
Max
8.0
8.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns