ADSP-21266SKSTZ-2D Analog Devices Inc, ADSP-21266SKSTZ-2D Datasheet - Page 34

• Manufacturer Part Number: ADSP-21266SKSTZ-2D
• Description: IC,DSP,32-BIT,CMOS,QFP,144PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21266SKSTZ-2D

• Interface: DAI, SPI
• Clock Rate: 200MHz
• Non-volatile Memory: ROM (512 kB)
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 32b
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 200MHz
• Mips: 200
• Device Input Clock Speed: 200MHz
• Ram Size: 256KB
• Program Memory Size: 512KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21266
SPI Interface Protocol—Master
Table 32. SPI Interface Protocol—Master
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
SSPIDM
HSPIDM
SPICLKM
SPICHM
SPICLM
DDSPIDM
HDSPIDM
SDSCIM
HDSM
SPITDM
CPHASE = 1
CPHASE = 0
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
SPICLK
(CP = 0)
SPICLK
(CP = 1)
(INPUT)
(INPUT)
FLG3-0
MISO
MOSI
MOSI
MISO
t
S S P I D M
Data Input Valid to SPICLK Edge (Data Input Setup Time)
SPICLK Last Sampling Edge to Data Input Not Valid
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
FLAG3–0 OUT (SPI Device Select) Low to First SPICLK Edge
Last SPICLK Edge to FLAG3–0 OUT High
Sequential Transfer Delay
t
S D S C I M
VALID
MSB
t
t
MSB
S P I C H M
S P IC LM
VALID
MSB
t
H S P ID M
t
t
D D S P I D M
t
t
S S P ID M
MSB
S P IC LM
S P I C H M
Figure 26. SPI Interface Protocol—Master
t
D D S P I D M
Rev. C | Page 34 of 44 | October 2007
t
H S P I D M
t
H D S P I D M
t
t
S S P I D M
HDSPIDM
t
VALID
S P IC LK M
LSB
LSB
VALID
LSB
Min
5
2
8 × t
4 × t
4 × t
10
4 × t
4 × t
4 × t
t
H D S M
LSB
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
t
– 2
– 2
– 2
– 1
– 1
H S P I D M
t
S P I T D M
Max
3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns