ADSP-21266SKSTZ-2D Analog Devices Inc, ADSP-21266SKSTZ-2D Datasheet - Page 20

• Manufacturer Part Number: ADSP-21266SKSTZ-2D
• Description: IC,DSP,32-BIT,CMOS,QFP,144PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21266SKSTZ-2D

• Interface: DAI, SPI
• Clock Rate: 200MHz
• Non-volatile Memory: ROM (512 kB)
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 32b
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 200MHz
• Mips: 200
• Device Input Clock Speed: 200MHz
• Ram Size: 256KB
• Program Memory Size: 512KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-21266
Reset
See
Table 14. Reset
1
Interrupts
The timing specification in
FLAG0, FLAG1, and FLAG2 pins when they are configured as
IRQ0, IRQ1, and IRQ2 interrupts. Also applies to DAI_P20–1
pins when configured as interrupts.
Table 15. Interrupts
Core Timer
The timing specification in
FLAG3 when it is configured as the core timer (CTIMER).
Table 16. Core Timer
Parameter
Timing Requirements
t
t
Parameter
Timing Requirement
t
Parameter
Switching Characteristic
t
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming
WRST
SRST
IPW
WCTIM
stable VDD and CLKIN (not including start-up time of external clock oscillator).
(C TIM E R )
Table 14
F L G 3
and
Figure
RESET Pulse Width Low
RESET Setup Before CLKIN Low
IRQx Pulse Width
CTIMER Pulse Width
10.
RESET
CLKIN
Table 15
Table 16
and
and
DAI_P20–1
1
Figure 11
Figure 12
(FLG2–0)
(IRQ2–0)
applies to the
Rev. C | Page 20 of 44 | October 2007
applies to
Figure 12. Core Timer
Figure 11. Interrupts
Figure 10. Reset
t
WRST
Min
4 × t
8
t
IPW
Min
4 × t
CK
CCLK
t
W C T IM
– 1
Min
2 t
CCLK
+2
t
SRST
Max
Max
Max
Unit
ns
ns
Unit
ns
Unit
ns