ADSP-21266SKSTZ-2D Analog Devices Inc, ADSP-21266SKSTZ-2D Datasheet - Page 32

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ADSP-21266SKSTZ-2D

Manufacturer Part Number
ADSP-21266SKSTZ-2D
Description
IC,DSP,32-BIT,CMOS,QFP,144PIN,PLASTIC
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Fixed/Floating Pointr

Specifications of ADSP-21266SKSTZ-2D

Interface
DAI, SPI
Clock Rate
200MHz
Non-volatile Memory
ROM (512 kB)
On-chip Ram
256kB
Voltage - I/o
3.30V
Voltage - Core
1.20V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
144-LQFP
Device Core Size
32b
Architecture
Super Harvard
Format
Floating Point
Clock Freq (max)
200MHz
Mips
200
Device Input Clock Speed
200MHz
Ram Size
256KB
Program Memory Size
512KB
Operating Supply Voltage (typ)
1.2/3.3V
Operating Supply Voltage (min)
1.14/3.13V
Operating Supply Voltage (max)
1.26/3.47V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADSP-21266SKSTZ-2D
Manufacturer:
Analog Devices Inc
Quantity:
10 000
ADSP-21266
Input Data Port (IDP)
The timing requirements for the IDP are given in
Figure
DAI_P20–1 pins using the SRU. Therefore, the timing specifica-
tions provided below are valid at the DAI_P20–1 pins.
Table 30. Input Data Port (IDP)
1
Parameter
Timing Requirements
t
t
t
t
t
t
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via the precision clock generators (PCG) or SPORTs. PCG input can be either
SISFS
SIHFS
SISD
SIHD
IDPCLKW
IDPCLK
CLKIN or any of the DAI pins.
24. IDP Signals (SCLK, FS, SDATA) are routed to the
FS Setup Before SCLK Rising Edge
FS Hold After SCLK Rising Edge
SData Setup Before SCLK Rising Edge
SData Hold After SCLK Rising Edge
Clock Width
Clock Period
DAI_P20
DAI_P20
DAI_P20
(SDATA)
(SCLK)
(FS)
1
1
1
1
Table 30
1
Rev. C | Page 32 of 44 | October 2007
1
Figure 24. Input Data Port (IDP)
1
and
t
IDPCLKW
t
SISFS
t
SISD
SAMPLE EDGE
Min
2.5
2.5
2.5
2.5
7
20
t
t
SIHFS
SIHD
Max
Unit
ns
ns
ns
ns
ns
ns

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