ADSP-21266SKSTZ-2D Analog Devices Inc, ADSP-21266SKSTZ-2D Datasheet - Page 19

• Manufacturer Part Number: ADSP-21266SKSTZ-2D
• Description: IC,DSP,32-BIT,CMOS,QFP,144PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21266SKSTZ-2D

• Interface: DAI, SPI
• Clock Rate: 200MHz
• Non-volatile Memory: ROM (512 kB)
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Device Core Size: 32b
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 200MHz
• Mips: 200
• Device Input Clock Speed: 200MHz
• Ram Size: 256KB
• Program Memory Size: 512KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Clock Input
See
Table 13. Clock Input
1
2
3
Clock Signals
The ADSP-21266 can use an external clock or a crystal. See
CLKIN pin description. The programmer can configure the
ADSP-21266 to use its internal clock generator by connecting
the necessary components to CLKIN and XTAL.
the component connections used for a crystal operating in fun-
damental mode. Note that the 200 MHz clock rate is achieved
using a 12.5 MHz crystal and a PLL multiplier ratio 16:1
(CCLK:CLKIN).
Parameter
Timing Requirements
t
t
t
t
t
Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in PMCTL.
Applies only for CLK_CFG1–0 = 01 and default values for PLL control bits in PMCTL.
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t
CK
CKL
CKH
CKRF
CCLK
CLKIN
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. CRYSTAL
SELECTION MUST COMPLY WITH CLKCFG1-0 = 10 OR = 01.
Table 13
Figure 9. 150 MHz or 200 MHz Operation with a 12.5 MHz
C1
CLKIN
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V – 2.0 V)
CCLK Period
and
Figure
Fundamental Mode Crystal
1M
X1
Figure 8. Clock Input
3
t
8.
CKH
C2
XTAL
t
CK
t
CKL
Min
7.5
7.5
6.66
20
Figure 9
1
1
1
Rev. C | Page 19 of 44 | October 2007
shows
150 MHz
Max
160
80
80
3
10
2
2
2
CCLK
.
Min
15
6
6
5
1
1
1
200 MHz
Max
160
80
80
3
10
2
2
2
ADSP-21266
Unit
ns
ns
ns
ns
ns