ADSP-21262SBBC-150 Analog Devices Inc, ADSP-21262SBBC-150 Datasheet - Page 24

• Manufacturer Part Number: ADSP-21262SBBC-150
• Description: IC,DSP,32-BIT,CMOS,BGA,136PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21262SBBC-150

• Interface: DAI, SPI
• Clock Rate: 150MHz
• Non-volatile Memory: ROM (512 kB)
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 136-CSPBGA
• Device Core Size: 32/40Bit
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 150MHz
• Mips: 150
• Device Input Clock Speed: 150MHz
• Ram Size: 256KB
• Program Memory Size: 512KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 136
• Package Type: CSPBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ADSP-21261/ADSP-21262/ADSP-21266
Memory Read—Parallel Port
The specifications in
Figure 17
memory-mapped peripherals) when the ADSP-2126x is access-
ing external memory space.
Table 25. 8-Bit Memory Read Cycle
1
Parameter
Timing Requirements
t
t
t
Switching Characteristics
t
t
t
t
t
t
t
D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × t
H = t
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
DRS
DRH
DAD
ALEW
ALERW
ADAS
ADAH
ALEHZ
RW
ADRH
1
1
1
CCLK
(if a hold cycle is specified, else H = 0)
are for asynchronous interfacing to memories (and
Address/Data 7–0 Setup Before RD High
Address/Data 7–0 Hold After RD High
Address 15–8 to Data Valid
ALE Pulse Width
ALE Deasserted to Read/Write Asserted
Address/Data 15–0 Setup Before ALE Deasserted
Address/Data 15–0 Hold After ALE Deasserted
ALE Deasserted to Address/Data7–0 in High-Z
RD Pulse Width
Address/Data 15–8 Hold After RD High
AD15 - 8
AD7 - 0
Table
ALE
WR
RD
25,
Table
26,
Figure
VALID ADDRESS
VALID ADDRESS
t
ADAS
t
ALEW
16, and
Figure 16. 8-Bit Memory Read Cycle
Rev. F | Page 24 of 44 | July 2009
t
ADAH
t
ALEHZ
t
ALERW
CCLK
Min
3.3
0
2 × t
1 × t
2.5 × t
0.5 × t
0.5 × t
D – 2
0.5 × t
CCLK
CCLK
t
DAD
CCLK
CCLK
CCLK
CCLK
VALID ADDRESS
– 2
– 0.5
– 2.0
– 0.8
– 0.8
– 1 + H
t
VALID DATA
RW
t
DRS
t
t
DRH
ADRH
Max
D + 0.5 × t
0.5 × t
CCLK
+ 2.0
CCLK
– 3.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns