ADSP-21262SBBC-150 Analog Devices Inc, ADSP-21262SBBC-150 Datasheet - Page 21

IC,DSP,32-BIT,CMOS,BGA,136PIN,PLASTIC

ADSP-21262SBBC-150

Manufacturer Part Number
ADSP-21262SBBC-150
Description
IC,DSP,32-BIT,CMOS,BGA,136PIN,PLASTIC
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Fixed/Floating Pointr

Specifications of ADSP-21262SBBC-150

Interface
DAI, SPI
Clock Rate
150MHz
Non-volatile Memory
ROM (512 kB)
On-chip Ram
256kB
Voltage - I/o
3.30V
Voltage - Core
1.20V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
136-CSPBGA
Device Core Size
32/40Bit
Architecture
Super Harvard
Format
Floating Point
Clock Freq (max)
150MHz
Mips
150
Device Input Clock Speed
150MHz
Ram Size
256KB
Program Memory Size
512KB
Operating Supply Voltage (typ)
1.2/3.3V
Operating Supply Voltage (min)
1.14/3.13V
Operating Supply Voltage (max)
1.26/3.47V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
136
Package Type
CSPBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADSP-21262SBBC-150
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Timer WDTH_CAP Timing
The timing specification in
Timer in WDTH_CAP (pulse width count and capture) mode.
Timer signals are routed to the DAI_P20–1 pins through the
SRU. Therefore, the timing specifications provided below are
valid at the DAI_P20–1 pins.
Table 21. Timer Width Capture Timing
DAI Pin-to-Pin Direct Routing
See
example, DAI_PB01_I to DAI_PB02_O).
Table 22. DAI Pin-to-Pin Routing
Parameter
Timing Requirements
t
Parameter
Timing Requirements
t
PWI
DPIO
DAI_P20–1
Table 22
(TIMER)
and
Timer Pulse Width
Figure 13
Delay DAI Pin Input Valid to DAI Output Valid
for direct pin connections only (for
Table 21
and
Figure 12
DAI_Pm
DAI_Pn
Figure 13. DAI Pin-to-Pin Direct Routing
Figure 12. Timer Width Capture Timing
applies to
Rev. F | Page 21 of 44 | July 2009
Min
2 × t
CCLK
t
PWI
t
DPIO
ADSP-21261/ADSP-21262/ADSP-21266
Min
1.5
Max
2(2
31
– 1) × t
CCLK
Max
10
Unit
ns
Unit
ns

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