ADSP-21060KS-160 Analog Devices Inc, ADSP-21060KS-160 Datasheet - Page 32
![Digital Signal Processor IC](/photos/6/71/67190/sp-240-2_sml.jpg)
ADSP-21060KS-160
Manufacturer Part Number
ADSP-21060KS-160
Description
Digital Signal Processor IC
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Floating Pointr
Datasheets
1.ADSP-21062KSZ-133.pdf
(64 pages)
2.ADSP-21060KS-160.pdf
(47 pages)
3.ADSP-21060KS-160.pdf
(64 pages)
Specifications of ADSP-21060KS-160
Supply Voltage Max
5.25V
Dsp Type
Fixed / Floating Point
Mounting Type
Surface Mount
Package / Case
240-MQFP
Memory Organization - Ram
4M
Rohs Status
RoHS non-compliant
Interface
Host Interface, Link Port, Serial Port
Clock Rate
40MHz
Non-volatile Memory
External
On-chip Ram
512kB
Voltage - I/o
5.00V
Voltage - Core
5.00V
Operating Temperature
0°C ~ 85°C
Device Core Size
32b
Architecture
Super Harvard
Format
Floating Point
Clock Freq (max)
40MHz
Mips
40
Device Input Clock Speed
40MHz
Ram Size
512KB
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.75V
Operating Supply Voltage (max)
5.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
MQFP
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-21060KS-160
Manufacturer:
AD
Quantity:
5 510
Company:
Part Number:
ADSP-21060KS-160
Manufacturer:
SHARP
Quantity:
5 510
Company:
Part Number:
ADSP-21060KS-160
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Link Ports: 1 × CLK Speed Operation
Parameter
Receive
Timing Requirements:
t
t
t
t
t
Switching Characteristics:
t
t
t
t
Transmit
Timing Requirements:
t
t
Switching Characteristics:
t
t
t
t
t
t
t
t
Link Port Service Request Interrupts: 1 × and
2 × Speed Operations
Timing Requirements:
t
t
NOTES
1
2
ADSP-21060/ADSP-21060L
SLDCL
HLDCL
LCLKIW
LCLKRWL
LCLKRWH
DLAHC
DLALC
ENDLK
TDLK
SLACH
HLACH
DLCLK
DLDCH
HLDCH
LCLKTWL
LCLKTWH
DLACLK
ENDLK
TDLK
SLCK
HLCK
LACK will go low with t
Only required for interrupt recognition in the current cycle.
Data Setup before LCLK Low
Data Hold after LCLK Low
LCLK Period (1 × Operation)
LCLK Width Low
LCLK Width High
LACK High Delay after CLKIN High
LACK Low Delay after LCLK High
LACK Enable from CLKIN
LACK Disable from CLKIN
LACK Setup before LCLK High
LACK Hold after LCLK High
LCLK Delay after CLKIN (1 × operation)
Data Delay after LCLK High
Data Hold after LCLK High
LCLK Width Low
LCLK Width High
LCLK Low Delay after LACK High
LDAT, LCLK Enable after CLKIN
LDAT, LCLK Disable after CLKIN
LACK/LCLK Setup before CLKIN Low
LACK/LCLK Hold after CLKIN Low
DLALC
relative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver’s link buffer is not about to fill.
1
2
2
Min
5 + DT/2
5 + DT/2
3.5
3
t
6
5
18 + DT/2
–3
18
–7
–3
(t
(t
(t
10
2
CK
CK
CK
CK
/2) – 2
/2) – 2
/2) + 8.5
ADSP-21060
Max
28.5 + DT/2
13
20 + DT/2
15.5
3
(t
(t
(3 × t
20 + DT/2
CK
CK
/2) + 2
/2) + 2
CK
/2) + 17 (t
Min
3
3
t
6
5
18 + DT/2
–3
5 + DT/2
20
–7
–3
(t
(t
5 + DT/2
10
2
CK
CK
CK
CK
/2) – 1
/2) – 1.25
/2) + 8.0
ADSP-21060L
Max
28.5 + DT/2
13
20 + DT/2
16.5
2.5
(t
(t
(3 × t
20 + DT/2
CK
CK
/2) + 1.25
/2) + 1.0
CK
/2) + 17.5 ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns