ADSP-21060KS-160 Analog Devices Inc, ADSP-21060KS-160 Datasheet - Page 29

• Manufacturer Part Number: ADSP-21060KS-160
• Description: Digital Signal Processor IC
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Floating Pointr

Specifications of ADSP-21060KS-160

• Supply Voltage Max: 5.25V
• Dsp Type: Fixed / Floating Point
• Mounting Type: Surface Mount
• Package / Case: 240-MQFP
• Memory Organization - Ram: 4M
• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 512kB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: 0°C ~ 85°C
• Device Core Size: 32b
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 40MHz
• Mips: 40
• Device Input Clock Speed: 40MHz
• Ram Size: 512KB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: MQFP
• Lead Free Status / Rohs Status: Not Compliant

Parameter
Timing Requirements:
t
t
Switching Characteristics:
t
t
t
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
Three-State Timing—Bus Master, Bus Slave, HBR, SBTS
These specifications show how the memory interface is disabled
(stops driving) or enabled (resumes driving) relative to CLKIN
STSCK
HTSCK
MIENA
MIENS
MIENHG
MITRA
MITRS
MITRHG
DATEN
DATTR
ACKEN
ACKTR
ADCEN
ADCTR
MTRHBG
MENHBG
Strobes = RD, WR, SW, PAGE, DMAG.
In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.
Memory Interface = Address, RD, WR, MSx, SW, HBG, PAGE, DMAGx, BMS (in EPROM boot mode).
INTERFACE
MEMORY
SBTS Setup before CLKIN
SBTS Hold before CLKIN
Address/Select Enable after CLKIN
Strobes Enable after CLKIN
HBG Enable after CLKIN
Address/Select Disable after CLKIN
Strobes Disable after CLKIN
HBG Disable after CLKIN
Data Enable after CLKIN
Data Disable after CLKIN
ACK Enable after CLKIN
ACK Disable after CLKIN
ADRCLK Enable after CLKIN
ADRCLK Disable after CLKIN
Memory Interface Disable before
HBG Low
Memory Interface Enable after
HBG High
HBG
MEMORY INTERFACE = ADDRESS, RD, WR, MSx, SW, PAGE, DMAGx. BMS (IN EPROM BOOT MODE)
3
3
INTERFACE
MEMORY
ADRCLK
CLKIN
DATA
SBTS
ACK
2
2
2
2
1
t
t
1
MIENA,
ADCEN
t
MENHBG
t
MIENS,
t
ACKEN
t
DATEN
t
MIENHG
Min
12 + DT/2
–1.5 – DT/8
–1.5 – DT/8
–1.5 – DT/8
9 + 5DT/16
0 – DT/8
7.5 + DT/4
–1 – DT/8
–2 – DT/8
0 + DT/8
19 + DT
ADSP-21060
t
STSCK
and the SBTS pin. This timing is applicable to bus master tran-
sition cycles (BTC) and host transition cycles (HTC) as well as
the SBTS pin.
Max
6 + DT/2
0 – DT/4
1.5 – DT/4
2.0 – DT/4
7 – DT/8
6 – DT/8
8 – DT/4
t
HTSCK
t
t
ADCTR
MITRA,
t
t
ADSP-21060/ADSP-21060L
DATTR
ACKTR
SBTS
t
MITRS,
Min
12 + DT/2
–1.25 – DT/8
–1.5 – DT/8
–1.5 – DT/8
9 + 5DT/16
0 – DT/8
7.5 + DT/4
–1 – DT/8
–2 – DT/8
0 + DT/8
19 + DT
t
MITRHG
ADSP-21060L
Max
6 + DT/2
0 – DT/4
1.5 – DT/4
2.0 – DT/4
7 – DT/8
6 – DT/8
8 – DT/4
t
MTRHBG
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns