ADN4604ASVZ-RL Analog Devices Inc, ADN4604ASVZ-RL Datasheet - Page 36

• Manufacturer Part Number: ADN4604ASVZ-RL
• Description: 4.25Gbps 16x16 Crossbar Switch
• Manufacturer: Analog Devices Inc
• Series: XStream™r

Specifications of ADN4604ASVZ-RL

• Function: Crosspoint Switch
• Circuit: 1 x 16:16
• On-state Resistance: 56 Ohm
• Voltage Supply Source: Single Supply
• Voltage - Supply, Single/dual (±): 2.7 V ~ 3.6 V
• Current - Supply: 95mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADN4604
PRINTED CIRCUIT BOARD (PCB) LAYOUT
GUIDELINES
The high speed differential inputs and outputs should be routed
with 100 Ω controlled impedance differential transmission
lines. The transmission lines, either microstrip or stripline,
should be referenced to a solid low impedance reference plane.
An example of a PCB cross-section is shown in Figure 55. The
trace width (W), differential spacing (S), height above reference
plane (H), and dielectric constant of the PCB material determine
the characteristic impedance. Adjacent channels should be kept
apart by a distance greater than 3 W to minimize crosstalk.
Thermal Paddle Design
The TQFP is designed with an exposed thermal paddle to
conduct heat away from the package and into the PCB. By
incorporating thermal vias into the PCB thermal paddle,
heat is dissipated more effectively into the inner metal layers
of the PCB. To ensure device performance at elevated
temperatures, it is important to have a sufficient number of
thermal vias incorporated into the design. An insufficient
number of thermal vias results in a θ
specified in Table 1.
It is recommended that a via array of 4 × 4 or 5 × 5 with a
diameter of 0.3 mm to 0.33 mm be used to set a pitch between
1.0 mm and 1.2 mm. A representative of these arrays is shown in
Figure 56.
SOLDERMASK
SIGNAL (MICROSTRIP)
PCB DIELECTRIC
REFERENCE PLANE
PCB DIELECTRIC
SIGNAL (STRIPLINE)
PCB DIELECTRIC
REFERENCE PLANE
PCB DIELECTRIC
Figure 55. Example of a PCB Cross-Section
Figure 56. PCB Thermal Paddle and Via
W
W
JA
value larger than
THERMAL
VIA
THERMAL
PADDLE
S
S
W
W
H
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Stencil Design for the Thermal Paddle
To effectively remove heat from the package and to enhance
electrical performance, the thermal paddle must be soldered
(bonded) to the PCB thermal paddle, preferably with minimum
voids. However, eliminating voids may not be possible because
of the presence of thermal vias and the large size of the thermal
paddle for larger size packages. Also, outgassing during the
reflow process may cause defects (splatter, solder balling) if the
solder paste coverage is too big.
It is recommended that smaller multiple openings in the stencil
be used instead of one big opening for printing solder paste on
the thermal paddle region. This typically results in 50% to 80%
solder paste coverage. Figure 57 shows how to achieve these
levels of coverage.
Voids within solder joints under the exposed paddle can have
an adverse affect on high speed and RF applications, as well as
on thermal performance. Because the package incorporates a
large center paddle, controlling solder voiding within this
region can be difficult. Voids within this ground plane can
increase the current path of the circuit. The maximum size for
a void should be less than via pitch within the plane. This
assures that any one via is not rendered ineffectual when any
void increases the current path beyond the distance to the next
available via.
Figure 57. Typical Thermal Paddle Stencil Design
1.35mm × 1.35mm SQUARES
AT 1.65mm PITCH
COVERAGE: 68%