ADN4604ASVZ-RL Analog Devices Inc, ADN4604ASVZ-RL Datasheet
ADN4604ASVZ-RL
Specifications of ADN4604ASVZ-RL
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ADN4604ASVZ-RL Summary of contents
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FEATURES DC to 4.25 Gbps per port NRZ data rate Programmable receive equalization 12 dB boost at 2 GHz Compensates 40 inches of FR4 at 4.25 Gbps Programmable transmit preemphasis/deemphasis boost at 4.25 Gbps Compensates 40 ...
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ADN4604 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Electrical Specifications ............................................................... Timing Specifications ............................................................ 4 SPI Timing Specifications ...
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SPECIFICATIONS ELECTRICAL SPECIFICATIONS TTIx TTOx input swing = 800 mV p- 27°C, unless otherwise noted. A Table 1. Parameter Conditions DYNAMIC PERFORMANCE Data Rate ...
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ADN4604 Parameter Conditions THERMAL CHARACTERISTICS Operating Temperature Range θ Still air; JEDEC 4-layer test board JA θ Still air JB θ At the exposed pad JC LOGIC CHARACTERISTICS Input High Voltage Threshold ( Input Low Voltage Threshold ...
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SPI TIMING SPECIFICATIONS SCK SDI SDO SCK t SDI SDO Table 3. SPI Timing Specifications Parameter SCK Clock Frequency ...
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ADN4604 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating 3 3 TTIE TTIW TTON TTOS CC 1 Internal Power Dissipation ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 100 99 RESET 1 PIN 1 IP0 2 IN0 IP1 5 IN1 TTIW IP2 8 IN2 IP3 11 IN3 IP4 ...
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ADN4604 Table 5. Pin Function Descriptions Pin No. Mnemonic 1 RESET 2 IP0 3 IN0 4, 13, 22, 35, 41, 54, 63 72, 85 IP1 6 IN1 TTIW 8 IP2 9 IN2 10, ...
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Pin No. Mnemonic 57 TTIE 58 IP10 59 IN10 61 IP11 62 IN11 64 IP12 65 IN12 67 IP13 68 IN13 70 IP14 71 IN14 73 IP15 74 IN15 75 SDA/SDO 76 SCL/SCK 77 OP8 78 ON8 80 ...
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ADN4604 TYPICAL PERFORMANCE CHARACTERISTICS TTIx TTOx input swing = 800 mV p- 27°C, unless otherwise noted. A 0.167IU/DIV REFERENCE EYE DIAGRAM AT TP1 0.167IU/DIV ...
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DATA OUT PATTERN GENERATOR 0.167IU/DIV REFERENCE EYE DIAGRAM AT TP1 0.167IU/DIV Figure 12. 4.25 Gbps Input Eye, 20 Inch FR4 Input Channel (TP2 from Figure 11) 0.167IU/DIV Figure 13. 4.25 Gbps Input Eye, 40-Inch FR4 Input Channel (TP2 from Figure ...
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ADN4604 DATA OUT PATTERN GENERATOR 0.167IU/DIV REFERENCE EYE DIAGRAM AT TP1 0.167IU/DIV Figure 17. 4.25 Gbps Output Eye, 20-Inch FR4 Output Channel (TP3 from Figure 16) 0.167IU/DIV Figure 18. 4.25 Gbps Output Eye, 40-Inch FR4 Input ...
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EQ = 0dB 12dB DATA RATE (Gbps) Figure 21. Deterministic Jitter vs. Data Rate 100 0dB 12dB 0 2.5 2.6 ...
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ADN4604 100 0dB 12dB INPUT FR4 TRACE LENGTH (Inches) Figure 27. Deterministic Jitter vs. Input FR4 Channel Length 100 ...
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FALL TIME 60 50 RISE TIME –40 – TEMPERATURE (°C) Figure 33. Rise/Fall Time vs. Temperature 1000 950 900 850 800 EQ = 12dB 750 ...
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ADN4604 THEORY OF OPERATION INTRODUCTION The ADN4604 × 16, buffered, asynchronous crosspoint switch that provides input equalization, output preemphasis, and output level programming capabilities. The receivers integrate an equalizer that is optimized to compensate for typical backplane ...
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SWITCH CORE The ADN4604 switch core is a fully nonblocking 16 × 16 array that allows multicast and broadcast configurations. The config- uration of the switch core is programmed through the serial control interface. The crosspoint configuration map controls the ...
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ADN4604 Table 9. XPT Control Registers Register Name Address Bit Update 0x80 0 Map Table Select 0x81 0 XPT Broadcast 0x82 3:0 XPT Map 0 Control 0 0x90 7:4 3:0 XPT Map 0 Control 1 0x91 7:4 3:0 XPT Map ...
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TRANSMITTERS Output Structure and Output Levels The ADN4604 transmitter outputs incorporate 50 Ω termin- ation resistors, ESD protection, and output current switches. Each channel provides independent control of both the absolute output level and the preemphasis output level. Note that ...
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ADN4604 Table 11 displays the TX Basic Control register. The TX Basic Control register consists of one byte (8 bits) for each of the 16 output channels. Each TX Basic Control register has the same functionality. The mapping of register ...
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Advanced Settings In addition to the basic settings provided in the TX basic control registers, advanced settings are available in TX Drive 0 Control and TX Drive 1 Control registers (Address 0x30 to Address 0x4F). The advanced settings are useful ...
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ADN4604 Table 15 displays the TX advanced control registers. The TX advanced control registers consist of two bytes (16 bits) for each of the 16 output channels. The mapping of register address to output channel is shown in the first ...
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TERMINATION The inputs and outputs include integrated 50 Ω termination resistors. For applications that require external termination resistors, the internal resistors can be disabled. For example, disabling the integrated 50 Ω termination resistors allows alternative termination values such as 75 ...
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ADN4604 SERIAL CONTROL INTERFACE The ADN4604 register set is controlled through a 2-wire I 2 interface. The ADN4604 acts only the I C bus in the system needs to include ...
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ADN4604 DATA READ To read data from the ADN4604 register set, a microcontroller any other I C master must send the appropriate control signals to the ADN4604 slave device. The steps are listed below; 2 ...
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ADN4604 SPI SERIAL CONTROL INTERFACE The SPI serial interface of the ADN4604 consists of four wires SCK, SDI, and SDO used to select the device when more than one device is connected to the serial clock ...
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CS SCK SDI ADDRESS SDO CS SCK SDI ADDRESS HI-Z SDO DATA BYTE 0 DATA BYTE 1 HI-Z Figure 49. SPI Continuous Write Sequence XXXXXXXX XXXXXXXX DATA BYTE 0 DATA BYTE 1 Figure 50. SPI Continuous Read Sequence Rev. 0 ...
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ADN4604 REGISTER MAP Registers repeated per port or per table entry are grouped together. Register address mapping is shown in the first column. Table 18. Register Map Address: Channel Default Register Name 0x00 N/A RESET 0x10 0xFF RX EQ Control ...
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Address: Channel Default Register Name 0x18: Broadcast, 0x00 TX basic control 0x20: Output 0, 0x21: Output 1, 0x22: Output 2, 0x23: Output 3, 0x24: Output 4, 0x25: Output 5, 0x26: Output 6, 0x27: Output 7, 0x28: Output 8, 0x29: Output ...
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ADN4604 Address: Channel Default Register Name 0x61: Table Entry 0 0x00 TX Lookup Table 1 0x63: Table Entry 1 0x99 0x65: Table Entry 2 0xCC 0x67: Table Entry 3 0xFF 0x69: Table Entry 4 0xFF 0x6B: Table Entry 5 0xFF ...
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Address: Channel Default Register Name 0xB0 0xEF XPT Status 0 0xB1 0xCD XPT Status 1 0xB2 0xAB XPT Status 2 0xB3 0x89 XPT Status 3 0xB4 0x67 XPT Status 4 0xB5 0x45 XPT Status 5 0xB6 0x23 XPT Status 6 ...
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ADN4604 APPLICATIONS INFORMATION The ADN4604 is an asynchronous and protocol agnostic digital switch and, therefore, is applicable to a wide range of applica- tions including network routing and digital video switching. The ADN4604 supports the data rates and signaling levels ...
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O O ADN4604 16 × 16 CROSSPOINT SWITCH O Figure 52. ADN4604 Networking Switch Application Block Diagram 8 LANE UPLINK PATH LANE DOWNLINK PATH ASIC ...
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ADN4604 SUPPLY SEQUENCING Ideally, all power supplies should be brought up to the appropri- ate levels simultaneously (power supply requirements are set by the supply limits in Table 1 and the absolute maximum ratings listed in Table 4). If the ...
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Table 19. Output Voltage Range and Output Common-Mode Shift vs. Output Level and PE Setting Single-Ended Output Levels and Register PE Boost Settings Boost PE TX SW-DC SW-PE (mV) (mV) % (dB) Drive 0 100 ...
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ADN4604 PRINTED CIRCUIT BOARD (PCB) LAYOUT GUIDELINES The high speed differential inputs and outputs should be routed with 100 Ω controlled impedance differential transmission lines. The transmission lines, either microstrip or stripline, should be referenced to a solid low impedance ...
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Large voids in the thermal paddle area should be avoided. To control voids in the thermal paddle area, solder masking may be required for thermal vias to prevent solder wicking inside the via during reflow, thus displacing the solder away ...
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... SEATING PLANE 25 26 0.20 0.09 7° 3.5° 0° 0.50 BSC ORDERING GUIDE Model Temperature Range ADN4604ASVZ 1 −40°C to +85°C 1 ADN4604ASVZ-RL −40°C to +85°C 1 ADN4604-EVALZ RoHS Compliant Part . 14.00 BSC PIN 1 TOP VIEW (PINS DOWN 1.05 1.00 ...
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NOTES Rev Page ADN4604 ...
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ADN4604 NOTES 2 Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I Rights to use these components system, ...