ADF4157BRUZ-RL Analog Devices Inc, ADF4157BRUZ-RL Datasheet - Page 17

• Manufacturer Part Number: ADF4157BRUZ-RL
• Description: IC,FREQUENCY SYNTHESIZER,CMOS,TSSOP,16PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Fractional N Synthesizer (RF)r

Specifications of ADF4157BRUZ-RL

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 6GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 6GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4157EB1Z - BOARD EVALUATION FOR ADF4157
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TEST REGISTER (R4) MAP
With R4[2:0] set to 100, the on-chip test register (R4) is
programmed as shown in Figure 21.
Negative Bleed Current
Setting Bits DB[24:23] to 11 turns on the constant negative
bleed current. This ensures that the charge pump operates out
of the dead zone. Thus the phase noise is not degraded and the
level of spurs is lower. Enabling constant negative bleed current
is particularly important on channels close to multiple PFD
frequencies.
DB31
0
DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
RESERVED
0
0
NB2
0
1
0
0
NB1
0
1
0
C2
0
0
NEGATIVE BLEED CURRENT
OFF
ON
NB2 NB1
BLEED
CURR-
NEG
ENT
C1
0
1
CLOCK DIVIDER MODE
CLOCK DIVIDER OFF
SWITCHED R FASTLOCK ENABLE
0
0
C2
MODE
CLK
DIV
C1
Figure 21. Test Register (R4) Map
D12
Rev. A | Page 17 of 24
D11 D10
D9
D8
CLK Divider Mode
Setting Bits DB[20:19] to 01 enables switched R fastlock.
12-Bit Clock Divider Value
Bits DB[18:7] are used to program the clock divider, which
determines for how long the loop remains in wideband mode
while the switched R fastlock technique is used.
Reserved Bits
All reserved bits should be set to 0 for normal operation.
12-BIT CLOCK DIVIDER VALUE
D12
0
0
0
0
.
.
.
1
1
1
1
D7
D11
0
0
0
0
.
.
.
1
1
1
1
D6
.......... D2
.......... 0
.......... 0
.......... 1
.......... 1
.......... .
.......... .
.......... .
.......... 0
.......... 0
.......... 1
.......... 1
D5
D4
D3
D1
0
1
0
1
.
.
.
0
1
0
1
D2
CLOCK DIVIDER VALUE
0
1
2
3
.
.
.
4092
4093
4094
4095
D1
0
RESERVED
0
0
0
C3(1) C2(0) C1(0)
CONTROL
BITS
ADF4157