ADF4157BRUZ-RL Analog Devices Inc, ADF4157BRUZ-RL Datasheet - Page 12

• Manufacturer Part Number: ADF4157BRUZ-RL
• Description: IC,FREQUENCY SYNTHESIZER,CMOS,TSSOP,16PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Fractional N Synthesizer (RF)r

Specifications of ADF4157BRUZ-RL

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 6GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 6GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4157EB1Z - BOARD EVALUATION FOR ADF4157
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADF4157
FRAC/INT REGISTER (R0) MAP
With R0[2:0] set to 000, the on-chip FRAC/INT register is
programmed as shown in Figure 17.
Reserved Bit
The reserved bit should be set to 0 for normal operation.
MUXOUT
The on-chip multiplexer is controlled by Bits DB[30:27] on the
ADF4157. See Figure 17 for the truth table.
12-Bit INT Value
These 12 bits control what is loaded as the INT value. This is
used to determine the overall feedback division factor. It is used
DB31
M4
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
M4
M3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CONTROL
MUXOUT
M3
M2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
M2
M1
M1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
N12
OUTPUT
THREE-STATE OUTPUT
DV
DGND
R DIVIDER OUTPUT
N DIVIDER OUTPUT
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
SERIAL DATA OUTPUT
RESERVED
RESERVED
CLK DIVIDER OUTPUT
RESERVED
FASTLOCK SWITCH
R DIVIDER/2
N DIVIDER/2
RESERVED
N11
DD
N12
0
0
0
0
1
1
1
.
.
.
N10
N11
12-BIT INTEGER VALUE (INT)
0
0
0
0
1
1
1
.
.
.
N9
N8
N10
0
0
0
0
1
1
1
.
.
.
N7
N9
0
0
0
0
1
1
1
.
.
.
N6
Figure 17. FRAC/INT Register (R0) Map
N8
N5
0
0
0
0
1
1
1
.
.
.
N4
N7
0
0
0
0
1
1
1
.
.
.
Rev. A | Page 12 of 24
N3
N6
0
0
0
0
1
1
1
.
.
.
N2
N5
1
1
1
1
1
1
1
.
.
.
N1
N4
F25
0
1
1
1
1
1
1
in Equation 1. See the INT, FRAC, and R Relationship section
for more information.
12-Bit MSB FRAC Value
These 12 bits, along with Bits DB[27:15] in the LSB FRAC
register (R1), control what is loaded as the FRAC value into
the fractional interpolator. This is part of what determines the
overall feedback division factor. It is also used in Equation 1.
These 12 bits are the most significant bits (MSB) of the 25-bit
FRAC value, and Bits DB[27:15] in the LSB FRAC register (R1)
are the least significant bits (LSB). See the RF Synthesizer: A
Worked Example section for more information.
.
.
.
F24
N3
1
0
0
0
1
1
1
.
.
.
*THE FRAC VALUE IS MADE UP OF THE 12-BIT MSB STORED IN
REGISTER 0, AND THE 13-BIT LSB REGISTER STORED IN
REGISTER 1. FRAC VALUE = 13-BIT LSB + 12-BIT MSB × 2
F23
F12
0
0
0
0
1
1
1
1
.
.
.
12-BIT MSB FRACTIONAL VALUE
N2
1
0
0
1
0
1
1
.
.
.
F22
F11
0
0
0
0
1
1
1
1
.
.
.
N1
1
0
1
0
1
0
1
F21
.
.
.
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
F20
INTEGER VALUE
(INT)
23
24
25
26
.
.
.
4093
4094
4095
(FRAC)
F19
F2
0
0
1
1
0
0
1
1
.
.
.
F18
F17
F1
0
1
0
1
0
1
0
1
.
.
.
F16
MSB FRACTIONAL VALUE
(FRAC)*
0
1
2
3
.
.
.
4092
4093
4094
4095
F15
F14 C3(0) C2(0) C1(0)
CONTROL
BITS
13
.