ADF4157BRUZ-RL Analog Devices Inc, ADF4157BRUZ-RL Datasheet
ADF4157BRUZ-RL
Specifications of ADF4157BRUZ-RL
Related parts for ADF4157BRUZ-RL
ADF4157BRUZ-RL Summary of contents
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FEATURES RF bandwidth to 6 GHz 25-bit fixed modulus allows subhertz frequency resolution 2 3.3 V power supply Separate V allows extended tuning voltage P Programmable charge pump currents 3-wire serial interface Digital lock detect Power-down mode Pin ...
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ADF4157 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Specifications .................................................................. 4 Absolute Maximum Ratings ............................................................ 5 Thermal Resistance ...................................................................... 5 ESD ...
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SPECIFICATIONS 2 3 dBm referred to 50 Ω. Table 1. Parameter B Version RF CHARACTERISTICS ( Input Frequency (RF ) 0.5/6.0 IN REFERENCE CHARACTERISTICS REF ...
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ADF4157 TIMING SPECIFICATIONS 2 3 dBm referred to 50 Ω. Table 2. Parameter Limit MIN MAX ...
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ABSOLUTE MAXIMUM RATINGS T = 25°C, GND = AGND = DGND = Table 3. Parameter AV /DV to AGND/DGND AGND/DGND / ...
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ADF4157 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS SET CPGND 3 14 ADF4157 TOP VIEW AGND 4 13 (Not to Scale REF ...
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TSSOP LFCSP Pin No. Pin No. Mnemonic 15 16 (EPAD) 21 (EPAD) Exposed Pad (EPAD) Description Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane should be ...
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ADF4157 TYPICAL PERFORMANCE CHARACTERISTICS PFD = 25 MHz, loop bandwidth = 20 kHz, reference = 100 MHz, I phase noise system –5 – 4/5 –15 –20 –25 –30 –35 – ...
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CIRCUIT DESCRIPTION REFERENCE INPUT SECTION The reference input stage is shown in Figure 11. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are open. This ensures ...
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ADF4157 PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP The PFD takes inputs from the R counter and the N counter and produces an output proportional to the phase and fre- quency difference between them. Figure simplified schematic ...
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REGISTER MAPS MUXOUT 12-BIT INTEGER VALUE (INT) CONTROL DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 ...
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ADF4157 FRAC/INT REGISTER (R0) MAP With R0[2:0] set to 000, the on-chip FRAC/INT register is programmed as shown in Figure 17. Reserved Bit The reserved bit should be set to 0 for normal operation. MUXOUT The on-chip multiplexer is controlled ...
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LSB FRAC REGISTER (R1) MAP With R1[2:0] set to 001, the on-chip LSB FRAC register is programmed as shown in Figure 18. 13-Bit LSB FRAC Value These 13 bits, along with Bits DB[14:3] in the INT/FRAC register (R0), control what ...
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ADF4157 R DIVIDER REGISTER (R2) MAP With R2[2:0] set to 010, the on-chip R divider register is programmed as shown in Figure 19. CSR Enable Setting this bit to 1 enables cycle slip reduction. This is a method for improving ...
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DBB CURRENT SETTING DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CPI4 ...
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ADF4157 FUNCTION REGISTER (R3) MAP With R3[2:0] set to 011, the on-chip function register is programmed as shown in Figure 20. Reserved Bits All reserved bits should be set to 0 for normal operation. Σ-Δ Reset For most applications, DB14 ...
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TEST REGISTER (R4) MAP With R4[2:0] set to 100, the on-chip test register (R4) is programmed as shown in Figure 21. Negative Bleed Current Setting Bits DB[24:23 turns on the constant negative bleed current. This ensures that the ...
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ADF4157 APPLICATIONS INFORMATION INITIALIZATION SEQUENCE After powering up the part, this programming sequence must be followed: 1. Test register (R4) 2. Function register (R3 divider register (R2) 4. LSB FRAC register (R1) 5. FRAC/INT register (R0) RF SYNTHESIZER: ...
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FASTLOCK TIMER AND REGISTER SEQUENCES If the fastlock mode is used, a timer value needs to be loaded into the PLL to determine the time spent in wide bandwidth mode. When Bits DB[20:19] in Register 4 (R4) are set to ...
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ADF4157 the input reference to avoid a possible feedthrough path on the board. LOW FREQUENCY APPLICATIONS The specification on the RF input is 0.5 GHz minimum; however, RF frequencies lower than this can be used, providing the mini- mum slew ...
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... Description 1 ADF4157BRUZ 16-Lead Thin Shrink Small Outline Package [TSSOP] 1 ADF4157BRUZ-RL 16-Lead Thin Shrink Small Outline Package [TSSOP] 1 ADF4157BRUZ-RL7 16-Lead Thin Shrink Small Outline Package [TSSOP] ADF4157BCPZ 1 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 1 ADF4157BCPZ-RL 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] ...
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ADF4157 NOTES Rev Page ...
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NOTES Rev Page ADF4157 ...
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ADF4157 NOTES ©2007–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05874-0-1/09(A) Rev Page ...