ADF4156BRUZ-RL Analog Devices Inc, ADF4156BRUZ-RL Datasheet - Page 6

• Manufacturer Part Number: ADF4156BRUZ-RL
• Description: IC,FREQUENCY SYNTHESIZER,CMOS,TSSOP,16PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Fractional N Synthesizer (RF)r

Specifications of ADF4156BRUZ-RL

• Design Resources: Low-Noise Microwave fractional-N PLL using active loop filter and RF prescaler (CN0174)
• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 6GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 6GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADF4156
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin No.
LFCSP
19
20
1
2, 3
4
5
6, 7
8
9, 10
11
12
13
14
15
16, 17
18
CPGND
AGND
RF
RF
REF
AV
R
SET
IN
IN
Figure 3. TSSOP Pin Configuration
CP
DD
IN
B
A
Mnemonic
R
CP
CPGND
AGND
RF
RF
AV
REF
DGND
CE
CLOCK
DATA
LE
MUXOUT
DV
V
SET
P
IN
IN
DD
1
2
3
4
5
6
7
8
DD
IN
B
A
(Not to Scale)
ADF4156
TOP VIEW
Description
Connecting a resistor between this pin and ground sets the maximum charge-pump output current. The
relationship between I
where R
Charge-Pump Output. When enabled, this pin provides ±I
the external VCO.
Charge-Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
Complementary Input to the RF Prescaler. Decouple this point to the ground plane with a small bypass
capacitor, typically 100 pF.
Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO.
Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane should be
placed as close as possible to this pin. AV
Reference Input. This is a CMOS input with a nominal threshold of V
of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
Digital Ground.
Chip Enable. A logic low on this pin powers down the device and puts the charge-pump output into
three-state mode.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the shift register on the CLOCK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the three LSBs serving as the control bits. This
input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one of the
five latches. The control bits are used to select the latch.
Multiplexer Output. This multiplexer output allows either the RF lock detect, the scaled RF, or the scaled
reference frequency to be accessed externally.
Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane should be
placed as close as possible to this pin. DV
Charge-Pump Power Supply. This should be greater than or equal to V
be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.
15
14
13
12
11
10
16
9
I
CPmax
V
DV
MUXOUT
LE
DATA
CLOCK
CE
DGND
P
SET
DD
= 5.1 kΩ and I
=
25
R
SET
5 .
CP
CPmax
and R
Rev. A | Page 6 of 24
= 5 mA.
SET
is
DD
DD
has a value of 3 V ± 10%. AV
has a value of 3 V ± 10%. DV
CPGND
AGND
AGND
RF
RF
CP
IN
IN
Figure 4. LFCSP Pin Configuration
B
A
to the external loop filter, which in turn drives
1
2
3
4
5
(Not to Scale)
ADF4156
DD
DD
TOP VIEW
DD
PIN 1
INDICATOR
/2 and an equivalent input resistance
must have the same voltage as DV
must have the same voltage as AV
DD
. In systems where V
15 MUXOUT
14 LE
13 DATA
12 CLOCK
11 CE
DD
is 3 V, it can
DD
DD
.
.