ADF4156BRUZ-RL Analog Devices Inc, ADF4156BRUZ-RL Datasheet - Page 11

• Manufacturer Part Number: ADF4156BRUZ-RL
• Description: IC,FREQUENCY SYNTHESIZER,CMOS,TSSOP,16PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Fractional N Synthesizer (RF)r

Specifications of ADF4156BRUZ-RL

• Design Resources: Low-Noise Microwave fractional-N PLL using active loop filter and RF prescaler (CN0174)
• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 6GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 6GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FRAC/INT REGISTER, R0
With the control bits (Bits[2:0]) of Register R0 set to 000, the
on-chip FRAC/INT register is programmed. Figure 17 shows
the input data format for programming this register.
12-Bit Integer Value (INT)
These 12 bits control what is loaded as the INT value. This
determines the overall feedback division factor. It is used in
Equation 1 (see the INT, FRAC, MOD, and R Relationship
section).
SERVED
M4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
DB31
RE-
0
M3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
M4
MUXOUT CONTROL
M2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
M3
M1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
M2
OUTPUT
THREE-STATE OUTPUT
DV
DGND
R-DIVIDER OUTPUT
N-DIVIDER OUTPUT
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
SERIAL DATA OUTPUT
RESERVED
RESERVED
CLOCK DIVIDER
RESERVED
FAST-LOCK SWITCH
R-DIVIDER/2
N-DIVIDER/2
RESERVED
DD
M1
N12
0
0
0
0
.
.
.
1
1
1
N12
N11
0
0
0
0
.
.
.
1
1
1
N11
N10
0
0
0
0
.
.
.
1
1
1
N10
N9
0
0
0
0
.
.
.
1
1
1
N9
N8
0
0
0
0
.
.
.
1
1
1
12-BIT INTEGER VALUE (INT)
N8
N7
0
0
0
0
.
.
.
1
1
1
N7
N6
0
0
0
0
.
.
.
1
1
1
N6
N5
1
1
1
1
.
.
.
1
1
1
Figure 17. FRAC/INT Register (R0) Map
N5
N4
0
1
1
1
.
.
.
1
1
1
N4
N3
1
0
0
0
.
.
.
1
1
1
Rev. A | Page 11 of 24
N3
N2
1
0
0
1
.
.
.
0
1
1
N2
N1
1
0
1
0
.
.
.
1
0
1
N1
12-Bit Fractional Value (FRAC)
These 12 bits control what is loaded as the FRAC value into
the fractional interpolator. This is part of what determines the
overall feedback division factor. It is also used in Equation 1.
The FRAC value must be less than the value loaded into the
MOD register.
MUXOUT
The on-chip multiplexer is controlled by DB30, DB29, DB28,
and DB27 on the ADF4156. See Figure 17 for the truth table.
INTEGER VALUE (INT)
23
24
25
26
.
.
.
4093
4094
4095
F12
F12
0
0
0
0
.
.
.
1
1
1
1
F11
F11
0
0
0
0
.
.
.
1
1
1
1
F10
.......... F2
.......... 0
.......... 0
.......... 1
.......... 1
.......... .
.......... .
.......... .
.......... 0
.......... 0
.......... 1
.........
12-BIT FRACTIONAL VALUE (FRAC)
F9
1
F8
0
1
0
1
.
.
.
0
1
0
1
F1
F7
FRACTIONAL VALUE (FRAC)
0
1
2
3
.
.
.
4092
4093
4094
4095
F6
F5
F4
F3
F2
F1 C3(0) C2(0) C1(0)
ADF4156
CONTROL
BITS