ADF4156BRUZ-RL Analog Devices Inc, ADF4156BRUZ-RL Datasheet - Page 16

• Manufacturer Part Number: ADF4156BRUZ-RL
• Description: IC,FREQUENCY SYNTHESIZER,CMOS,TSSOP,16PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Fractional N Synthesizer (RF)r

Specifications of ADF4156BRUZ-RL

• Design Resources: Low-Noise Microwave fractional-N PLL using active loop filter and RF prescaler (CN0174)
• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 6GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 6GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADF4156
CLK DIV REGISTER, R4
With the control bits (Bits[2:0]) of Register R3 set to 100, the
on-chip clock divider register (R4) is programmed. Figure 21
shows the input data format for programming this register.
12-Bit Clock Divider Value
The 12-bit clock divider value sets the timeout counter for
activation of the fast-lock mode or a phase resync. See the Phase
Resync section for more information.
Clock Divider Mode
DB[20:19] control the mode of the clock divider in the ADF4156.
These bits should be set to 01 to activate the fast-lock mode, or
to 10 to activate a phase resync. In most applications, neither a
fast lock nor a phase resync is required. In this case, DB[20:19]
should be set to 00.
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
0
0
0
0
RESERVED
0
0
0
0
M2
0
0
1
1
0
M1
0
1
0
1
0
CLK DIV MODE
CLK DIV OFF
FAST-LOCK MODE
RESYNC TIMER ENABLED
RESERVED
M2
MODE
CLK
DIV
M1
Figure 21. CLK DIV Register (R4) Map
D12
Rev. A | Page 16 of 24
D11
D10
D9
12-BIT CLOCK DIVIDER VALUE
D12
0
0
0
0
.
.
.
1
1
1
1
RESERVED BITS
All reserved bits should be set to 0 for normal operation.
INITIALIZATION SEQUENCE
After powering up the part, the correct register programming
sequence is as follows:
1.
2.
3.
4.
5.
D8
D11
0
0
0
0
.
.
.
1
1
1
1
CLK DIV register (R4)
Function register (R3)
MOD/R register (R2)
Phase register (R1)
FRAC/INT register (R0)
D7
.......... D2
.......... 0
.......... 0
.......... 1
.......... 1
.......... .
.......... .
.......... .
.......... 0
.......... 0
.......... 1
.......... 1
D6
D5
D1
0
1
0
1
.
.
.
0
1
0
1
D4
D3
CLOCK DIVIDER VALUE
0
1
2
3
.
.
.
4092
4093
4094
4095
D2
D1
R4
RESERVED
R3
R2
R1 C3(1) C2(0) C1(0)
CONTROL
BITS