ADF4156BRUZ-RL Analog Devices Inc, ADF4156BRUZ-RL Datasheet - Page 3

• Manufacturer Part Number: ADF4156BRUZ-RL
• Description: IC,FREQUENCY SYNTHESIZER,CMOS,TSSOP,16PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Fractional N Synthesizer (RF)r

Specifications of ADF4156BRUZ-RL

• Design Resources: Low-Noise Microwave fractional-N PLL using active loop filter and RF prescaler (CN0174)
• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: Yes/No
• Frequency - Max: 6GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Frequency-max: 6GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPECIFICATIONS
AV
Table 1.
Parameter
RF CHARACTERISTICS
REFERENCE CHARACTERISTICS
PHASE DETECTOR
CHARGE PUMP
LOGIC INPUTS
LOGIC OUTPUTS
POWER SUPPLIES
NOISE CHARACTERISTICS
1
2
3
4
5
6
Operating temperature for B version: −40°C to +85°C.
AC coupling ensures AV
Guaranteed by design. Sample tested to ensure compliance.
This value can be used to calculate the phase noise for any application. Use the formula −211 + 10 log(f
seen at the VCO output. The value given is the lowest noise mode.
The phase noise is measured with the EVAL-ADF4156EBZ1 evaluation board and the Agilent E5500 phase noise system.
f
REFIN
RF Input Frequency (RF
REF
REF
REF
REF
Phase Detector Frequency
I
I
Matching
I
I
V
V
I
C
V
V
I
V
AV
DV
V
I
Low Power Sleep Mode
Normalized Phase Noise Floor
Phase Noise Performance
CP
CP
CP
CP
INH
OH
DD
DD
INH
INL
OH
OH
OL
P
IN
High Value
Low Value
Absolute Accuracy
R
5800 MHz Output
Three-State Leakage Current
, Output High Current
= 100 MHz, f
Sink/Source
vs. V
vs. Temperature
, Input Capacitance
DD
/I
DD
, Output Low Voltage
= DV
, Input Low Voltage
, Output High Voltage
, Output High Voltage
IN
IN
IN
IN
SET
, Input High Voltage
INL
Input Frequency
Input Sensitivity
Input Capacitance
Input Current
, Input Current
Range
CP
DD
= 2.7 V to 3.3 V, V
PFD
= 25 MHz, offset frequency = 5 kHz, RF
DD
/2 bias.
6
IN
)
5
3
P
4
= AV
DD
to 5.5 V, AGND = DGND = 0 V, T
B Version
0.5/6.0
10/250
0.4/AV
10
±100
32
5
312.5
2.5
2.7/10
1
2
2
2
1.4
0.6
±1
10
1.4
V
100
0.4
2.7/3.3
AV
AV
32
1
−211
−89
DD
OUT
DD
DD
− 0.4
= 5800 MHz, N = 232, loop bandwidth = 20 kHz, I
/5.5
DD
Rev. A | Page 3 of 24
Unit
GHz min/max
MHz min/max
V p-p min/max
pF max
μA max
MHz max
mA typ
μA typ
% typ
kΩ min/max
nA typ
% typ
% typ
% typ
V min
V max
μA max
pF max
V min
V min
μA max
V max
V min/max
V min/max
mA max
μA typ
dBc/Hz typ
dBc/Hz typ
A
= T
MIN
to T
PFD
MAX
) + 20 log N to calculate the in-band phase noise performance as
Test Conditions/Comments
−10 dBm min to 0 dBm max. For lower frequencies,
ensure slew rate (SR) > 400 V/μs.
For f < 10 MHz, use a dc-coupled CMOS-compatible
square wave, slew rate > 25 V/μs.
Biased at AV
Programmable.
With R
With R
Sink and source current.
0.5 V < V
0.5 V < V
V
Open-drain output chosen; 1 kΩ pull-up to 1.8 V.
CMOS output chosen.
I
26 mA typical.
@ VCO output.
@ 5 kHz offset, 25 MHz PFD frequency.
OL
, dBm referred to 50 Ω, unless otherwise noted.
CP
= 500 μA.
= V
CP
SET
SET
P
= 313 μA, and lowest noise mode.
/2.
CP
CP
= 5.1 kΩ.
= 5.1 kΩ.
< V
< V
DD
P
P
/2.
− 0.5.
− 0.5.
2
1
ADF4156