AD9983A/PCBZ Analog Devices Inc, AD9983A/PCBZ Datasheet - Page 37

• Manufacturer Part Number: AD9983A/PCBZ
• Description: Pb-free EVALUATION Kit AD9983A
• Manufacturer: Analog Devices Inc
• Series: Advantiv®r

Specifications of AD9983A/PCBZ

• Main Purpose: Video, Video Processing
• Embedded: No
• Utilized Ic / Part: AD9983A
• Primary Attributes: 3 x 8-Bit 140 MSPS ADC's
• Secondary Attributes: Integrated PLL & VCO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

0x24—Bit[2] SOGIN1 Detection Bit
This bit is used to indicate when activity is detected on the
SOGIN1 input pin. If SOG is held high or low, activity is not
detected. The sync processing block diagram shows where this
function is implemented. 0 = SOGIN1 not active. 1 = SOGIN1
is active.
Table 67. SOGIN1 Detection Results
Detect
0
1
0x24—Bit[1] COAST Detection Bit
This bit detects activity on the EXTCK/COAST pin. It indicates
that one of the two signals is active, but it does not indicate
which one. A dc signal is not detected.
Table 68. COAST Detection Result
Detect
0
1
0x24—Bit[0] CLAMP Detection Bit
This bit is used to indicate when activity is detected on the
external CLAMP pin. If external CLAMP is held high or low,
activity is not detected.
Table 69. CLAMP Detection Results
Detect
0
1
POLARITY STATUS
0x25—Bit[7] HSYNC0 Polarity
Indicates the polarity of HSYNC0 input.
Table 70. Detected HSYNC0 Polarity Results
Detect
0
1
0x25—Bit[6] HSYNC1 Polarity
Indicates the polarity of HSYNC1 input.
Table 71. Detected HSYNC1 Polarity Results
Detect
0
1
0x25—Bit[5] VSYNC0 Polarity
Indicates the polarity of VSYNC0 input.
Table 72. Detected VSYNC0 Polarity Results
Detect
0
1
Result
Hsync polarity is negative
Hsync polarity is positive
Result
Hsync polarity is negative
Hsync polarity is positive
Result
Vsync polarity is negative
Vsync polarity is positive
Result
No activity detected
Activity detected
Result
No activity detected
Activity detected
Result
No activity detected
Activity detected
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0x25—Bit[4] VSYNC1 Polarity
Indicates the polarity of VSYNC1 input.
Table 73. Detected VSYNC1 Polarity Results
Detect
0
1
0x25—Bit[3] COAST Polarity
Indicates the polarity of the external COAST signal.
Table 74. Detected COAST Polarity Results
Detect
0
1
0x25—Bit[2] CLAMP Polarity
Indicates the polarity of the CLAMP signal.
Table 75. Detected CLAMP Polarity Results
Detect
0
1
0x25—Bit[1] Extraneous Pulses Detection
A second output from the Hsync filter, this status bit tells
whether extraneous pulses are present on the incoming sync
signal. Often extraneous pulses are used for copy protection, so
this status bit can be used for this purpose.
Table 76. Equalization Pulse Detect Bit
Detect
0
1
HSYNC COUNT
0x26—Bits[7:0] Hsyncs per Vsync MSB
The 8 MSBs of the 12-bit counter that reports the number of
Hsyncs/Vsync on the active input. This is useful for determining
the mode and is an aid in setting the PLL divide ratio.
0x27—Bits[7:4] Hsyncs per Vsync LSBs
The 4 LSBs of the 12-bit counter that reports the number of
Hsyncs/Vsync on the active input.
TEST REGISTERS
0x28—Bits[7:0] Test Register 1
Must be written to 0xBF for proper operation.
0x29—Bits[7:0] Test Register 2
Must be written to 0x00 for proper operation.
0x2A—Bits[7:0] Test Register 3
Read-only bits for future use.
0x2B—Bits[7:0] Test Register 4
Read-only bits for future use.
No equalization pulses detected during active Hsync
Equalization pulses detected during active Hsync
Result
Result
Vsync polarity is negative
Vsync polarity is positive
Result
Coast polarity is negative
Coast polarity is positive
Result
Clamp polarity is negative
Clamp polarity is positive
AD9983A