AD9983A/PCBZ Analog Devices Inc, AD9983A/PCBZ Datasheet - Page 26

• Manufacturer Part Number: AD9983A/PCBZ
• Description: Pb-free EVALUATION Kit AD9983A
• Manufacturer: Analog Devices Inc
• Series: Advantiv®r

Specifications of AD9983A/PCBZ

• Main Purpose: Video, Video Processing
• Embedded: No
• Utilized Ic / Part: AD9983A
• Primary Attributes: 3 x 8-Bit 140 MSPS ADC's
• Secondary Attributes: Integrated PLL & VCO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9983A
Hex
Address
0x1F
0x20
0x21
0x22
Read/Write,
Read Only
R/W
R/W
R/W
R/W
Bits
3
2
1
0
7:5
4
3
2:1
0
7:6
5
4
3
2
1
0
7:0
7:0
Default
Value
**** 0***
**** *0**
**** **0*
**** ***0
100* ****
***1 ****
**** 0***
**** *10*
**** ***0
0*** ****
*0** ****
**0* ****
***0 ****
**** 1***
**** *0**
0010 0000
0011 0010
Register Name
Output Select 1
Output Select 2
Rev. 0 | Page 26 of 44
Description
Power-Down.
0 = Normal operation
1 = Power-down
Power-Down Pin Polarity.
0 = Active low
1 = Active high
Power-Down Fast Switching Control.
0 = Normal power-down operation
1 = The chip stays powered up and the outputs are put in high
impedance mode
SOGOUT High Impedance Control.
0 = SOGOUT operates as normal during power-down
1 = SOGOUT is in high impedance during power-down
Output Mode.
100 = 4:4:4 output mode
101 = 4:2:2 output mode
110 = 4:4:4—DDR output mode
Primary Output Enable.
0 = Primary output is in high impedance state
1 = Primary output is enabled
Secondary Output Enable.
0 = Secondary output is in high impedance state
1 = Secondary output is enabled
Output Drive Strength.
00 = Low output drive strength
01 = Medium output drive strength
10 = High output drive strength
11 = High output drive strength
Applies to all outputs except VSOUT.
Output Clock Invert.
0 = Noninverted pixel clock
1 = Inverted pixel clock
Applies to all clocks output on DATACK.
Output Clock Select.
00 = Pixel clock
01 = 90° phase shifted pixel clock
10 = 2× pixel clock
11 = 0.5× pixel clock
Output High Impedance.
0 = Normal outputs
1 = All outputs except SOGOUT in high impedance mode
SOG High Impedance.
0 = Normal SOG output
1 = SOGOUT pin is in high impedance mode
Field Output Polarity. Sets the polarity of the field output signal.
0 = Active low => even field, active high => odd field
1 = Active low => odd field, active high => even field
PLL Sync Filter Enable.
0 = PLL uses raw Hsync/SOG
1 = PLL uses filtered Hsync/SOG
Sync Processing Input Select. Selects the sync source for the sync
processor.
0 = Sync processing uses raw Hsync/SOGIN
1 = Sync processing uses regenerated Hsync from sync filter
Must be set to 1 for proper operation.
Must be set to default for proper operation.
Must be set to default for proper operation.