AD9983A/PCBZ Analog Devices Inc, AD9983A/PCBZ Datasheet - Page 19

• Manufacturer Part Number: AD9983A/PCBZ
• Description: Pb-free EVALUATION Kit AD9983A
• Manufacturer: Analog Devices Inc
• Series: Advantiv®r

Specifications of AD9983A/PCBZ

• Main Purpose: Video, Video Processing
• Embedded: No
• Utilized Ic / Part: AD9983A
• Primary Attributes: 3 x 8-Bit 140 MSPS ADC's
• Secondary Attributes: Integrated PLL & VCO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

HSYNC TIMING
The Hsync is processed in the AD9983A to eliminate ambiguity
in the timing of the leading edge with respect to the phase-
delayed pixel clock and data.
The Hsync input is used as a reference to generate the pixel
sampling clock. The sampling phase can be adjusted with
respect to Hsync through a full 360° in 32 steps via the phase
adjust register (to optimize the pixel sampling time). Display
systems use Hsync to align memory and display write cycles, so
it is important to have a stable timing relationship between
Hsync output (HSOUT) and the data clock (DATACK).
CB/CROUT
DATAOUT
HSYNCx
DATACK
HSYNCx
DATACK
DATAIN
DATACK
HSOUT
HSYNCx
DATAIN
HSOUT
DATAIN
HSOUT
YOUT
DDR NOTES
1. OUTPUT DATACK MAY BE DELAYED 1/4 CLOCK PERIOD IN THE REGISTERS.
2. SEE PROJECT DOCUMENT FOR VALUES OF F (FALLING EDGE) AND R (RISING EDGE).
3. FOR DDR 4:2:2 MODE: TIMING IS IDENTICAL, VALUES OF F AND R CHANGE.
GENERAL NOTES
1. DATA DELAY MAY VARY ± ONE CLOCK CYCLE, DEPENDING ON PHASE SETTING.
2. ADCs SAMPLE INPUT ON FALLING EDGE OF DATACK.
3. HSYNC SHOWN IS ACTIVE HIGH (EDGE SHOWN IS LEADING EDGE).
NOTES
1. PIXEL AFTER HSOUT CORRESONDS TO BLUE INPUT.
2. EVEN NUMBER OF PIXEL DELAY BETWEEN HSOUT AND DATAOUT.
P0
P0
P0
P1
P1
P1
P2
P2
P2
2 CLOCK CYCLE DELAY
2 CLOCK CYCLE DELAY
Figure 16. Double Data Rate (DDR) Timing Mode
2 CLOCK CYCLE DELAY
P3
P3
P3
Figure 14. 4:4:4 Timing Mode
Figure 15. 4:2:2 Timing Mode
P4
P4
P4
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P5
P5
P5
P6
P6
P6
Three things happen to Hsync in the AD9983A. First, the
polarity of Hsync input is determined and thus has a known
output polarity. The known output polarity can be programmed
either active high or active low (Register 0x12, Bit 3). Second,
HSOUT is aligned with DATACK and data outputs. Third, the
duration of HSOUT (in pixel clocks) is set via Register 0x13.
HSOUT is the sync signal that should be used to drive the rest
of the display system.
P7
P7
P7
F0 R0 F1 R1 F2 R2 F3 R3
P8
8 CLOCK CYCLE DELAY
P8
8 CLOCK CYCLE DELAY
P8
8 CLOCK CYCLE DELAY
CB0
P0
Y0
P9
P9
P9
CR0
P1
Y1
P10
P10
P10
CB2
P2
Y2
P11
P11
P11
CR2
P3
Y3
AD9983A