AD9852/PCBZ Analog Devices Inc, AD9852/PCBZ Datasheet - Page 33

• Manufacturer Part Number: AD9852/PCBZ
• Description: 300 Mhz C-DDS Synthesizer Eval Board
• Manufacturer: Analog Devices Inc
• Series: AgileRF™r
• Type: Synthesizerr

Specifications of AD9852/PCBZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: AD9852
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 10. Serial I/O Pin Requirements
Pin Number
1 to 8
14 to 16
17
18
19
20
21
22
A<5:0>
D<7:0>
A<5:0>
D<7:0>
RD
WR
D1
Mnemonic
D [7:0]
A [5:3]
A2/IO RESET
A1/SDO
A0/SDIO
I/O UD CLK
WR/SCLK
RD/CS
A1
A1
t
RDHOZ
SPECIFICATION
t
t
t
t
ADV
AHD
RDLOV
RDHOZ
t
D1
AHD
SPECIFICATION
t
t
t
t
t
t
t
t
ASU
DSU
ADH
DHD
WRLOW
WRHIGH
WR
WRHIGH
t
ASU
t
RDLOV
t
ADV
Serial I/O Description
The parallel data pins are not active; tie these pins to VDD or GND.
The A5, A4, and A3 parallel address pins are not active; tie these pins to VDD or GND.
IO RESET.
SDO.
SDIO.
Update Clock. Same functionality for serial mode as parallel mode.
SCLK.
CS—Chip Select.
VALUE
15ns
5ns
15ns
10ns
VALUE
8.0ns
3.0ns
0ns
0ns
2.5ns
7ns
10.5ns
Figure 49. Parallel Port Read Timing Diagram
Figure 50. Parallel Port Write Timing Diagram
DESCRIPTION
ADDRESS TO DATA VALID TIME (MAXIMUM)
ADDRESS HOLD TIME TO RD SIGNAL INACTIVE (MINIMUM)
RD LOW TO OUTPUT VALID (MAXIMUM)
RD HIGH TO DATA THREE-STATE (MAXIMUM)
t
DESCRIPTION
ADDRESS SETUP TIME TO WR SIGNAL ACTIVE
DATA SETUP TIME TO WR SIGNAL ACTIVE
ADDRESS HOLD TIME TO WR SIGNAL INACTIVE
DATA HOLD TIME TO WR SIGNAL INACTIVE
WR SIGNAL MINIMUM LOW TIME
WR SIGNAL MINIMUM HIGH TIME
MINIMUM WRITE TIME
WR
t
WRLOW
Rev. E | Page 33 of 52
A2
A2
D2
t
DSU
D2
t
AHD
t
DHD
A3
D3
A3
D3
AD9852