AD9779A-DPG2-EBZ Analog Devices Inc, AD9779A-DPG2-EBZ Datasheet - Page 47

• Manufacturer Part Number: AD9779A-DPG2-EBZ
• Description: Dual 16B, 1.0 GSPS TxDAC
• Manufacturer: Analog Devices Inc

Specifications of AD9779A-DPG2-EBZ

• Design Resources: Interfacing ADL5370 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0016) Interfacing ADL5371 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0017) Interfacing ADL5372 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0018) Interfacing ADL5373 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0019) Interfacing ADL5374 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0020) Interfacing ADL5375 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0021)
• Number Of Dac's: 2
• Number Of Bits: 16
• Outputs And Type: 2, Differential
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9779A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

POWER DISSIPATION
Figure 91 to Figure 99 show the power dissipation of the 1.8 V
and 3.3 V digital and clock supplies in single DAC and dual DAC
modes. In addition to this, the power dissipation/current of the
3.3 V analog supply (mode and speed independent) in single DAC
Figure 92. Power Dissipation, Digital 1.8 V Supply, I Data Only, Real Mode,
Figure 93. Power Dissipation, Clock 1.8 V Supply, I Data Only, Real Mode,
0.08
0.06
0.04
0.02
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.4
0.3
0.2
0.1
Includes Modulation Modes, Does Not Include Zero Stuffing
Figure 91. Total Power Dissipation, I Data Only, Real Mode
0
0
0
0
0
0
8× INTERPOLATION
25
25
25
8× INTERPOLATION,
ZERO STUFFING
8× INTERPOLATION
50
50
50
Does Not Include Zero Stuffing
75
75
75
100
100
100
f
f
f
DATA
DATA
DATA
8× INTERPOLATION
125
125
125
(MSPS)
(MSPS)
(MSPS)
4× INTERPOLATION,
4× INTERPOLATION
4× INTERPOLATION
ZERO STUFFING
150
150
150
2× INTERPOLATION
2× INTERPOLATION
1× INTERPOLATION
1× INTERPOLATION
175
175
175
2× INTERPOLATION,
1× INTERPOLATION,
4× INTERPOLATION
2× INTERPOLATION
1× INTERPOLATION
ZERO STUFFING
ZERO STUFFING
200
200
200
225
225
225
250
250
250
Rev. A | Page 47 of 60
mode is 102 mW/31 mA. In dual DAC mode, this is 182 mW/
55 mA. When the PLL is enabled, it adds 50 mA/90 mW to the
1.8 V clock supply.
Figure 96. Power Dissipation, Digital 1.8 V Supply, I and Q Data, Dual DAC
Figure 94. Power Dissipation, Digital 3.3 V Supply, I Data Only, Real Mode,
0.075
0.050
0.025
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
0
0
0
0
4× INTERPOLATION,
ZERO STUFFING
8× INTERPOLATION, f
Figure 95. Total Power Dissipation, Dual DAC Mode
8× INTERPOLATION,
ZERO STUFFING
ALL INTERPOLATION MODES
25
Includes Modulation Modes and Zero Stuffing
25
25
Mode, Does Not Include Zero Stuffing
50
NO MODULATION
50
50
AD9776A/AD9778A/AD9779A
75
75
75
100 125 150 175 200 225
2× INTERPOLATION,
ZERO STUFFING
f
f
DAC
DAC
DAC
100
100
f
f
f
DATA
DATA
DATA
/8,
/4,
/2,
8× INTERPOLATION, ALL
MODULATION MODES
125
125
(MSPS)
(MSPS)
(MSPS)
1× INTERPOLATION,
ZERO STUFFING
4× INTERPOLATION
150
150
1× INTERPOLATION,
NO MODULATION
2× INTERPOLATION,
ALL MODULATION MODES
2× INTERPOLATION
175
175
4× INTERPOLATION,
ALL MODULATION
MODES
1× INTERPOLATION
200
200
250 275
225
225
250
300
2
50