AD9779A-DPG2-EBZ Analog Devices Inc, AD9779A-DPG2-EBZ Datasheet - Page 44

• Manufacturer Part Number: AD9779A-DPG2-EBZ
• Description: Dual 16B, 1.0 GSPS TxDAC
• Manufacturer: Analog Devices Inc

Specifications of AD9779A-DPG2-EBZ

• Design Resources: Interfacing ADL5370 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0016) Interfacing ADL5371 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0017) Interfacing ADL5372 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0018) Interfacing ADL5373 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0019) Interfacing ADL5374 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0020) Interfacing ADL5375 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0021)
• Number Of Dac's: 2
• Number Of Bits: 16
• Outputs And Type: 2, Differential
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9779A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9776A/AD9778A/AD9779A
OPTIMIZING THE DATA INPUT TIMING
The AD9776A/AD9778A/AD9779A have on-chip circuitry that
enables the user to optimize the input data timing by adjusting
the relationship between the DATACLK output and DCLK_SMP,
the internal clock that samples the input data. This optimization
is made by a sequence of SPI register read and write operations.
The timing optimization can be done under strict control of the
user, or the device can be programmed to maintain a configur-
able timing margin automatically. Each of these methods is
detailed in the following section.
Figure 86 shows the circuitry that detects sample timing errors
and adjusts the data interface timing. The DCLK_SMP signal is
the internal clock used to latch the input data. Ultimately, it is
the rising edge of this signal that needs to be centered in the
valid sampling period of the input data. This is accomplished by
adjusting the time delay, t
timing and as a result, the arrival time of the input data with
respect to DCLK_SMP.
The error detect circuitry works by creating two sets of sampled
data (referred to as the margin test data) in addition to the
actual sampled data used in the device data path. One set of
sampled data is latched before the actual data sampling point.
The other set of sampled data is latched after the actual data
sampling point. If the margin test data match the actual data,
the sampling is considered valid and no error is declared. If
there is a mismatch between the actual data and the margin test
data an error is declared.
The Data Timing Margin<3:0> variable determines how much
before and after the actual data sampling point the margin test
data are latched. Therefore, the data timing margin variable
determines how much setup and hold margin the interface
needs for the data timing error IRQ to remain inactive (show
error free operation). Therefore, the timing error IRQ is set
whenever the setup and hold margins drop below the Data
Timing Margin<3:0> value and does not necessarily indicate
that the data latched into the device is incorrect.
In addition to setting the data timing error IRQ, the Data
Timing Error Type bit is indicated when an error occurs. The
Data Timing Error Type bit is set low to indicate a hold error
TIMING
MARGIN <3:0>
PD1<0>
DATACLK
DELAY<3:0>
DCLK_SMP
Figure 86. Timing Error Detection and Optimization Circuitry
Δ
t
M
Δ
Δ
t
t
M
D
D
, which changes the DATACLK
D
CLK
CLK
D
Q
Q
DETECTION
ERROR
TIMING
TIMING
ERROR IRQ
TIMING
ERROR TYPE
DATACLK
Rev. A | Page 44 of 60
and high to indicate a setup error. Figure 87 shows a timing
diagram of the data interface and the status of the Data Timing
Error Type bit.
Automatic Timing Optimization
When automatic timing optimization mode is enabled
(Register 0x03, Bit 7 = 1), the device continuously monitors
the Data Timing Error IRQ and Data Timing Error Type bits.
The DATACLK Delay<3:0> is increased if a setup error is
detected and decreased if a hold error is detected. The value of
the DATACLK Delay<3:0> setting currently in use can be read
back by the user.
Manual Timing Optimization
When the device is operating in manual timing optimization
mode (Register 0x03, Bit 7 = 0), the device does not alter the
DATACLK Delay<3:0> value from what is programmed by the
user. By default, the DATACLK Delay Enable is inactive. This
bit must be set high for the DATACLK Delay<3:0> value to be
realized. The delay (in absolute time) when programming
DATACLK delay between 00000 and 11111 varies from about
700 ps to about 6.5 ns. The typical delays per increment over
temperature are shown in Table 26.
Table 26. Data Delay Line Typical Delays Over Temperature
Delay
Zero Code Delay (Delay Upon
Average Unit Delay
In manual mode, the error checking logic is activated and
generates an interrupt if a setup/hold violation is detected. One
error check operation is performed per device configuration.
Any change to the Data Timing Margin<3:0> or DATACLK
Delay<3:0> values triggers a new error check operation.
Enabling Delay Line)
DATA
DATA
DATA
SAMPLING
DELAYED
DATA
Figure 87. Timing Diagram of Margin Test Data
SAMPLING
Δ
Δ
Δ
INSTANT
ACTUAL
t
t
t
M
M
M
Δ
Δ
Δ
t
t
t
M
M
M
SAMPLING
DELAYED
CLOCK
−40°C
630
175
TIMING ERROR = 0
TIMING ERROR = 1
DATA TIMING ERROR TYPE = 1
TIMING ERROR = 1
DATA TIMING ERROR TYPE = 0
+25°C
700
190
+85°C
740
210
Unit
ps
ps