AD9778ABSVZ Analog Devices Inc, AD9778ABSVZ Datasheet - Page 52

• Manufacturer Part Number: AD9778ABSVZ
• Description: IC,D/A CONVERTER,DUAL,14-BIT,CMOS,TQFP,100PIN
• Manufacturer: Analog Devices Inc

Specifications of AD9778ABSVZ

• Number Of Bits: 14
• Data Interface: Parallel
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 300mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Package: 100TQFP EP
• Resolution: 14 Bit
• Conversion Rate: 1 GSPS
• Architecture: Interpolation Filter
• Digital Interface Type: Parallel
• Number Of Outputs Per Chip: 2
• Output Type: Current
• Full Scale Error: ±2(Typ) %FSR
• Integral Nonlinearity Error: ±1.5(Typ) LSB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9778A-EBZ - BOARD EVALUATION AD9778A
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9776A/AD9778A/AD9779A
Figure 97. Power Dissipation, Clock 1.8 V Supply, I and Q Data, Dual DAC
0.075
0.050
0.025
0.125
0.100
0.075
0.050
0.025
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
Figure 98. Power Dissipation, Digital 3.3 V Supply, I and Q Data,
0
Figure 99. DVDD18 Power Dissipation of Inverse Sinc Filter
0
0
0
0
0
8× INTERPOLATION, f
ALL INTERPOLATION MODES
25
25
200
Mode, Does Not Include Zero Stuffing
NO MODULATION
50
50
75
75
400
Dual DAC Mode
f
f
DAC
DAC
DAC
100
100
f
f
f
DATA
DATA
DAC
/8,
/4,
/2,
600
125
125
(MSPS)
(MSPS)
(MSPS)
4× INTERPOLATION
150
150
1× INTERPOLATION,
800
NO MODULATION
2× INTERPOLATION
175
175
200
200
1000
225
225
1200
250
250
Rev. B | Page 52 of 56
POWER-DOWN AND SLEEP MODES
The AD9776A/AD9778A/AD9779A have a variety of power-down
modes; thus, the digital engine, main TxDACs, or auxiliary DACs
can be powered down individually or together. Via the 3-wire
interface port, the main TxDACs can be placed in sleep or power-
down mode. In sleep mode, the TxDAC output is turned off,
thus reducing power dissipation. The reference remains powered
on, however, so that recovery from sleep mode is very fast. With
the power-down mode bit set (Register 0x00, Bit 4), all analog
and digital circuitry, including the reference, is powered down.
The 3-wire interface port remains active in this mode. This
mode offers more substantial power savings than sleep mode,
but the turn-on time is much longer. The auxiliary DACs also
have the capability to be programmed into sleep mode via the
3-wire interface port. The auto power-down enable bit (Register
0x00, Bit 3) controls the power-down function for the digital
section of the devices. The auto power-down function works in
conjunction with the TXENABLE pin (Pin 39); see Table 31 for
details.
Table 31.
TXENABLE
(Pin 39)
0
1
Description
If auto power-down enable bit = 0, flush data
path with 0s.
If auto power-down enable bit = 1, flush data for
multiple REFCLK cycles; then, automatically
place the digital engine in power-down state.
DACs, reference, and 3-wire interface port are
not affected.
Normal operation.