AD9778ABSVZ Analog Devices Inc, AD9778ABSVZ Datasheet - Page 2

• Manufacturer Part Number: AD9778ABSVZ
• Description: IC,D/A CONVERTER,DUAL,14-BIT,CMOS,TQFP,100PIN
• Manufacturer: Analog Devices Inc

Specifications of AD9778ABSVZ

• Number Of Bits: 14
• Data Interface: Parallel
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 300mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Package: 100TQFP EP
• Resolution: 14 Bit
• Conversion Rate: 1 GSPS
• Architecture: Interpolation Filter
• Digital Interface Type: Parallel
• Number Of Outputs Per Chip: 2
• Output Type: Current
• Full Scale Error: ±2(Typ) %FSR
• Integral Nonlinearity Error: ±1.5(Typ) LSB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9778A-EBZ - BOARD EVALUATION AD9778A
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9776A/AD9778A/AD9779A
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Typical Signal Chain ......................................................................... 1
Revision History ............................................................................... 3
Functional Block Diagram .............................................................. 4
Specifications ..................................................................................... 5
Absolute Maximum Ratings ............................................................ 9
Pin Configurations and Function Descriptions ......................... 10
Typical Performance Characteristics ........................................... 16
Terminology .................................................................................... 24
Theory of Operation ...................................................................... 25
3-Wire Interface .............................................................................. 26
3-Wire Interface Register Map ...................................................... 28
Interpolation Filter Architecture .................................................. 33
DC Specifications ......................................................................... 5
Digital Specifications ................................................................... 6
Digital Input Data Timing Specifications ................................. 7
AC Specifications .......................................................................... 8
Thermal Resistance ...................................................................... 9
ESD Caution .................................................................................. 9
Differences Between AD9776/AD9778/ AD9779 and
AD9776A/AD9778A/AD9779A............................................... 25
General Operation of the Serial Interface ............................... 26
Instruction Byte .......................................................................... 26
Serial Interface Port Pin Descriptions ..................................... 27
MSB/LSB Transfers..................................................................... 27
Interpolation Filter Bandwidth Limits .................................... 37
Rev. B | Page 2 of 56
Sourcing the DAC Sample Clock ................................................. 39
Full-Scale Current Generation ..................................................... 43
Gain and Offset Correction .......................................................... 44
Input Data Ports ............................................................................. 46
Device Synchronization ................................................................. 49
Power Dissipation ........................................................................... 51
Evaluation Board Overview .......................................................... 53
Outline Dimensions ....................................................................... 55
Inverse Sinc Filter ....................................................................... 38
Direct Clocking .......................................................................... 39
Clock Multiplication .................................................................. 39
Driving the REFCLK Input ....................................................... 42
Internal Reference ...................................................................... 43
I/Q Channel Gain Matching ..................................................... 44
Auxiliary DAC Operation ......................................................... 44
LO Feedthrough Compensation .............................................. 45
Results of Gain and Offset Correction .................................... 45
Single Port Mode ........................................................................ 46
Dual Port Mode .......................................................................... 46
Input Data Referenced to DATACLK ...................................... 46
Input Data Referenced to REFCLK ......................................... 47
Optimizing the Data Input Timing .......................................... 48
Synchronization Logic Overview ............................................. 49
Synchronizing Devices to a System Clock .............................. 50
Interrupt Request Operation .................................................... 50
Power-Down and Sleep Modes................................................. 52
Evaluation Board Operation ..................................................... 53
Ordering Guide .......................................................................... 55