AD9778ABSVZ Analog Devices Inc, AD9778ABSVZ Datasheet - Page 38

• Manufacturer Part Number: AD9778ABSVZ
• Description: IC,D/A CONVERTER,DUAL,14-BIT,CMOS,TQFP,100PIN
• Manufacturer: Analog Devices Inc

Specifications of AD9778ABSVZ

• Number Of Bits: 14
• Data Interface: Parallel
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 300mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Package: 100TQFP EP
• Resolution: 14 Bit
• Conversion Rate: 1 GSPS
• Architecture: Interpolation Filter
• Digital Interface Type: Parallel
• Number Of Outputs Per Chip: 2
• Output Type: Current
• Full Scale Error: ±2(Typ) %FSR
• Integral Nonlinearity Error: ±1.5(Typ) LSB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9778A-EBZ - BOARD EVALUATION AD9778A
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9776A/AD9778A/AD9779A
As shown in Table 20, the mixing functions of most of the
modes result in cross-coupling of samples between the I and Q
channels. The I and Q channels only operate independently
with the f
the I and Q DAC outputs can only be done in the f
other modulation modes require complex input data and
produce complex output signals.
Table 20. Modulation Mixing Sequences
Modulation
f
f
−f
f
INVERSE SINC FILTER
The inverse sinc filter is implemented as a nine-tap FIR filter. It
is designed to provide less than ±0.05 dB pass-band ripple up to
a frequency of 0.4 × f
upper end of the pass band, the inverse sinc filter has an intrinsic
insertion loss of 3.4 dB. The transfer function is shown in
Figure 71 and the tap coefficients are given in Table 21.
DAC
DAC
DAC
DAC
/2
/4
/8
/4
S
/2 mode. This means that real modulation using both
Mixing Sequence
I = I, −I, I, −I, …
Q = Q, −Q, Q, −Q, …
I = I, Q, −I, −Q, …
Q = Q, −I, −Q, I, …
I = I, −Q, −I, Q, …
Q = Q, I, −Q, −I, …
I = I, r(I + Q), Q, r(−I + Q), −I, −r(I + Q), −Q, r(I − Q),
…
Q = Q, r(Q − I), −I, −r(Q + I), −Q, r(−Q + I), I, r(Q + I),
…
where r = √2/2
DATA
. To provide the necessary gain at the
S
/2 mode. All
Rev. B | Page 38 of 56
Table 21. Inverse Sinc Filter
Lower Coefficient
H(1)
H(2)
H(3)
H(4)
H(5)
The inverse sinc filter is disabled by default. It can be enabled by
setting the inverse sinc enable bit (Bit 3) in Register 0x02.
Figure 71. Transfer Function of Inverse Sinc Filter with the DAC sin(x)/x Output
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
0
0
0.05
0.10
COMBINED SINC AND SINC
0.15
Upper Coefficient
H(9)
H(8)
H(7)
H(6)
N/A
SINC
0.20 0.25
–1
f/f
RESPONSE
SAMPLE
0.30 0.35
–1
RESPONSE
0.40
Integer Value
+2
−4
+10
−35
+401
0.45 0.50